Jason e97e55dd63 AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator ...

`output_bin_count` is declared `reg [RP_RANGE_BIN_WIDTH_MAX-1:0]`
(9 bits on 50T, 12 bits on 200T), but the reset and ST_IDLE assignments
used the literal `9'd0`. Vivado zero-extends with a width-mismatch
warning on 200T. The FORMAL port `fv_output_bin_count` was also
hardcoded `[8:0]`.

Replace all three sites with `{RP_RANGE_BIN_WIDTH_MAX{1'b0}}` /
parameterized port width — same pattern already used for the
`range_bin_index` reset in this module.

No functional change. Verified by full FPGA regression: 41/41 PASS,
0 lint errors (Range Bin Decimator: 63 checks PASS).

2026-04-30 09:04:01 +05:45

..

constraints

xdc(200t): pin AD9484 OR LVDS pair to U20/V20 (L11_T1_SRCC_14)

2026-04-29 16:01:04 +05:45

formal

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ip/xfft_2048_ip

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scripts

chore: delete dead latency_buffer; doc cleanup for two stale comments

2026-04-28 12:52:13 +05:45

tb

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

.gitignore

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ad9484_interface_400m.v

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adc_clk_mmcm_integration.md

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adc_clk_mmcm.v

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cdc_modules.v

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cfar_ca.v

AUDIT-C7: document GO/SO edge-bin Pfa drift in cfar_ca header

2026-04-30 08:42:32 +05:45

chirp_memory_loader_param.v

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cic_decimator_4x_enhanced.v

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dac_interface_single.v

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ddc_400m.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

ddc_input_interface.v

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doppler_processor.v

doppler: gate S_IDLE→S_ACCUMULATE on frame_start_pulse (AUDIT-S3)

2026-04-29 18:36:31 +05:45

edge_detector.v

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fft_engine_axi_bridge.v

fft_engine_axi_bridge: respect axi_din_tready with 1-deep skid buffer

2026-04-29 17:24:21 +05:45

fft_engine.v

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fft_twiddle_16.mem

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fft_twiddle_1024.mem

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fft_twiddle_2048.mem

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fir_lowpass.v

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fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

frequency_matched_filter.v

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long_chirp_lut.mem

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long_chirp_seg0_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg0_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

matched_filter_multi_segment.v

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matched_filter_processing_chain.v

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mti_canceller.v

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nco_400m_enhanced.v

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plfm_chirp_controller.v

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

radar_mode_controller.v

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radar_params.vh

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radar_receiver_final.v

fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)

2026-04-29 19:37:37 +05:45

radar_system_top_50t.v

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radar_system_top_te0712_dev.v

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radar_system_top_te0713_dev.v

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radar_system_top_te0713_umft601x_dev.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_system_top.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_transmitter.v

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range_bin_decimator.v

AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator

2026-04-30 09:04:01 +05:45

run_regression.sh

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

rx_gain_control.v

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short_chirp_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

short_chirp_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

usb_data_interface_ft2232h.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

xfft_16.v

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xfft_2048.v

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