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cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

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matched_filter_processing_chain declared `input wire [5:0] chirp_counter`
but never read it inside the module. matched_filter_multi_segment passed
its own chirp_counter through to that dead port.

Removed the port from the chain and the corresponding hookup at the
multi_segment instantiation site. Five testbenches also referenced the
port (tb_mf_cosim, tb_matched_filter_processing_chain, tb_rxb_latency
_measure plus the four MF cosim variants that share tb_mf_cosim) — the
reg/connection/init lines were dropped, and the now-stale "Test Group 8:
Chirp Counter Passthrough" was repurposed as a port-removal smoke test
that confirms the chain still produces FFT_SIZE outputs without that
input.

multi_segment.chirp_counter input remains on the port list (it could
plausibly be wired to per-chirp logic in the future); it is now formally
unused but iverilog/Vivado do not flag unused module inputs.

Quick regression: 28/29 PASS (same as baseline; the 1 fail is the known
iverilog/Xilinx-IP RX-NEW-3 gap unchanged by this commit).
This commit is contained in:
Jason
2026-04-27 14:06:55 +05:45
parent 2c34323bcb
commit 0b8b933e27
5 changed files with 12 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/matched_filter_multi_segment.v
+5 -4
View File
@@ -528,10 +528,11 @@ matched_filter_processing_chain m_f_p_c(
.adc_data_i(fft_input_i),
.adc_data_q(fft_input_q),
.adc_valid(fft_input_valid),// && buffer_processing),
// Chirp Selection
.chirp_counter(chirp_counter),
// RX-A1: chain.chirp_counter removed (was unused inside the chain).
// multi_segment.chirp_counter input is now formally unused but kept
// on the port list for potential future per-chirp sequencing.
// Reference Chirp Memory Interface (single pair — upstream selects long/short)
.ref_chirp_real(ref_chirp_real),
.ref_chirp_imag(ref_chirp_imag),
9_Firmware/9_2_FPGA/matched_filter_processing_chain.v
+2 -3
View File
@@ -18,7 +18,6 @@
* Interface contract (from matched_filter_multi_segment.v line 361):
* .clk, .reset_n
* .adc_data_i, .adc_data_q, .adc_valid <- from input buffer
* .chirp_counter <- 6-bit frame counter
* .ref_chirp_real/imag <- reference (time-domain)
* .range_profile_i, .range_profile_q, .range_profile_valid -> output
* .chain_state -> 4-bit status
@@ -50,8 +49,8 @@ module matched_filter_processing_chain (
input wire [15:0] adc_data_q,
input wire adc_valid,
// Chirp counter (for future multi-chirp modes)
input wire [5:0] chirp_counter,
// RX-A1 (closed 2026-04-27): chirp_counter port removed — never read
// inside the chain. multi_segment passed it through to nothing.
// Reference chirp (time-domain, latency-aligned by upstream buffer)
// Upstream chirp_memory_loader_param selects long/short reference
9_Firmware/9_2_FPGA/tb/tb_matched_filter_processing_chain.v
+5 -7
View File
@@ -17,7 +17,6 @@ module tb_matched_filter_processing_chain;
reg [15:0] adc_data_i;
reg [15:0] adc_data_q;
reg adc_valid;
reg [5:0] chirp_counter;
reg [15:0] ref_chirp_real;
reg [15:0] ref_chirp_imag;
wire signed [15:0] range_profile_i;
@@ -80,7 +79,6 @@ module tb_matched_filter_processing_chain;
.adc_data_i (adc_data_i),
.adc_data_q (adc_data_q),
.adc_valid (adc_valid),
.chirp_counter (chirp_counter),
.ref_chirp_real (ref_chirp_real),
.ref_chirp_imag (ref_chirp_imag),
.range_profile_i (range_profile_i),
@@ -128,7 +126,6 @@ module tb_matched_filter_processing_chain;
adc_valid = 0;
adc_data_i = 16'd0;
adc_data_q = 16'd0;
chirp_counter = 6'd0;
ref_chirp_real = 16'd0;
ref_chirp_imag = 16'd0;
cap_enable = 0;
@@ -439,18 +436,19 @@ module tb_matched_filter_processing_chain;
check(cap_count == FFT_SIZE, "Frame 2: 2048 outputs");
// ════════════════════════════════════════════════════════
// TEST GROUP 8: Chirp counter passthrough
// TEST GROUP 8: RX-A1 port-removal smoke test
// (was "Chirp counter passthrough"; chain.chirp_counter port
// was removed because it was never read inside the chain.)
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 8: Chirp Counter Passthrough ---");
$display("\n--- Test Group 8: RX-A1 — chain runs without chirp_counter port ---");
apply_reset;
chirp_counter = 6'd42;
start_capture;
feed_dc_frame;
wait_for_idle;
cap_enable = 0;
$display(" Outputs: %0d", cap_count);
check(cap_count == FFT_SIZE, "Processes correctly with chirp_counter=42");
check(cap_count == FFT_SIZE, "Chain processes a frame after RX-A1 port removal");
// ════════════════════════════════════════════════════════
// TEST GROUP 9: Signal vs different reference
9_Firmware/9_2_FPGA/tb/tb_mf_cosim.v
-3
View File
@@ -87,7 +87,6 @@ reg signed [15:0] ref_mem_q [0:FFT_SIZE-1];
reg [15:0] adc_data_i;
reg [15:0] adc_data_q;
reg adc_valid;
reg [5:0] chirp_counter;
reg [15:0] ref_chirp_real;
reg [15:0] ref_chirp_imag;
@@ -105,7 +104,6 @@ matched_filter_processing_chain dut (
.adc_data_i(adc_data_i),
.adc_data_q(adc_data_q),
.adc_valid(adc_valid),
.chirp_counter(chirp_counter),
.ref_chirp_real(ref_chirp_real),
.ref_chirp_imag(ref_chirp_imag),
.range_profile_i(range_profile_i),
@@ -152,7 +150,6 @@ task apply_reset;
adc_data_i <= 16'd0;
adc_data_q <= 16'd0;
adc_valid <= 1'b0;
chirp_counter <= 6'd0;
ref_chirp_real <= 16'd0;
ref_chirp_imag <= 16'd0;
repeat(4) @(posedge clk);
9_Firmware/9_2_FPGA/tb/tb_rxb_latency_measure.v
-3
View File
@@ -31,7 +31,6 @@ module tb_rxb_latency_measure;
reg signed [15:0] adc_data_i;
reg signed [15:0] adc_data_q;
reg adc_valid;
reg [5:0] chirp_counter;
reg signed [15:0] ref_chirp_real;
reg signed [15:0] ref_chirp_imag;
wire signed [15:0] range_profile_i;
@@ -45,7 +44,6 @@ module tb_rxb_latency_measure;
.adc_data_i (adc_data_i),
.adc_data_q (adc_data_q),
.adc_valid (adc_valid),
.chirp_counter (chirp_counter),
.ref_chirp_real (ref_chirp_real),
.ref_chirp_imag (ref_chirp_imag),
.range_profile_i (range_profile_i),
@@ -121,7 +119,6 @@ module tb_rxb_latency_measure;
adc_data_i = 0;
adc_data_q = 0;
adc_valid = 0;
chirp_counter = 6'd0;
ref_chirp_real = 0;
ref_chirp_imag = 0;