Jason e97e55dd63 AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator ...

`output_bin_count` is declared `reg [RP_RANGE_BIN_WIDTH_MAX-1:0]`
(9 bits on 50T, 12 bits on 200T), but the reset and ST_IDLE assignments
used the literal `9'd0`. Vivado zero-extends with a width-mismatch
warning on 200T. The FORMAL port `fv_output_bin_count` was also
hardcoded `[8:0]`.

Replace all three sites with `{RP_RANGE_BIN_WIDTH_MAX{1'b0}}` /
parameterized port width — same pattern already used for the
`range_bin_index` reset in this module.

No functional change. Verified by full FPGA regression: 41/41 PASS,
0 lint errors (Range Bin Decimator: 63 checks PASS).

2026-04-30 09:04:01 +05:45

..

9_1_Microcontroller

mcu(health): poll PD15 + dispatch ERROR_FPGA_DSP_STALL (AUDIT-S10 follow-up)

2026-04-29 23:42:21 +05:45

9_2_FPGA

AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator

2026-04-30 09:04:01 +05:45

9_3_GUI

fix(usb): C-9 — GUI bulk-frame parser for FT2232H + clamp inert flag bits

2026-04-29 15:12:04 +05:45

tests/cross_layer

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

tools

…