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perf(fpga): symmetric pre-adder FIR — 32→16 DSPs/channel (-32 total)
Re-group the 32-tap symmetric lowpass into 16 (D+A)*B operations using the DSP48E1 pre-adder, exploiting coeff[k] == coeff[31-k]. Production silicon (XC7A50T) drops from 112/120 DSPs (93.3%) to 80/120 (66.7%), freeing the budget needed for the matched-filter FFT swap (RX-NEW-3). Bit-exact contract preserved at non-saturating signal levels: DC=5000 → 8847 and 45 MHz tone → ±16 LSB match the unfolded design and the Python golden model. Throughput unchanged (1 sample/cycle, 100 MSPS); latency +2 cycles for the pre-adder stage. Saturation thresholds rebuilt via bit concatenation to dodge the Verilog 32-bit-literal trap (1 <<< 34 silently wraps to 0, which made the earlier symmetric draft assert positive saturation on all non-negative accumulator values). Local regression: 32/34 PASS — same as baseline; the two failures (Receiver Integration, Matched Filter Chain) are pre-existing RX-NEW-3 (FFT throughput) and unaffected by this change.
This commit is contained in:
Jason
+135
-230
@@ -1,5 +1,47 @@
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`timescale 1ns / 1ps
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// ============================================================================
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// fir_lowpass_parallel_enhanced — 32-tap symmetric FIR, half-tap optimized
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// ============================================================================
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// Architecture: linear-phase symmetric FIR using the DSP48E1 pre-adder.
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// Because coeff[k] == coeff[31-k], the convolution is re-grouped into 16
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// pre-add+multiply operations:
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//
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// y[n] = sum_{k=0..15} h[k] * ( x[n-k] + x[n-31+k] )
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//
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// Each grouped tap uses ONE multiply (vs two in the naive layout), so the
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// FIR consumes 16 multiplies instead of 32. The pre-adder lives inside
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// the DSP48E1 (D + A) → B multiplier, so the savings collapse straight to
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// 16 DSP48E1 per channel.
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//
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// Why symmetric reduction rather than 4:1 polyphase folding:
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// The CIC `_4x` decimator runs in clk_400m and emits 100 M pulses/s,
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// which the cdc_adc_to_processing CDC carries into clk_100m as one
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// dst_valid per dst cycle in steady state. The FIR therefore receives
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// data at 100 MSPS, NOT 25 MSPS as an earlier comment incorrectly
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// claimed (see commit 977434a). Polyphase folding would drop samples
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// at this rate. Symmetric half-tap reduction preserves 1 sample/cycle
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// throughput and still gets the DSP halving.
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//
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// Bit-exact contract: produces the same 32-tap convolution result as the
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// previous unfolded design for inputs that don't overflow the saturation
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// threshold (±2^34). Verified against a Python golden model at the
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// existing test stimuli (DC=5000 → 8847; 45 MHz tone → ±16 LSB).
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//
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// Resource impact (target XC7A50T):
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// - DSP48E1: 32 → 16 per channel (saves 16 per channel; 32 across I/Q
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// = 27% of the 120-DSP budget freed for downstream FFT work)
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// - Throughput: unchanged (1 sample/cycle, fully pipelined)
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// - Latency: 11 cycles (was 9 — pre-adder costs 1 stage; tree depth same)
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//
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// Accumulator widths: the pre-adder grows the multiply input by 1 bit,
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// so the multiply product is 37-bit (was 36 unfolded). Sum of 16 such
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// products needs +4 bits → 41-bit accumulator. Saturation thresholds and
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// output bit-slice are unchanged from the unfolded design (compare against
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// ±2^(ACCUM_WIDTH-2) = ±2^34, slice [ACCUM_WIDTH-2 : DATA_WIDTH-1] =
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// [34:17]) so downstream signal levels and headroom stay the same.
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// ============================================================================
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module fir_lowpass_parallel_enhanced (
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input wire clk,
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input wire reset_n,
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@@ -11,87 +53,22 @@ module fir_lowpass_parallel_enhanced (
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output wire filter_overflow
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);
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parameter TAPS = 32;
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parameter COEFF_WIDTH = 18;
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parameter DATA_WIDTH = 18;
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parameter ACCUM_WIDTH = 36;
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parameter TAPS = 32;
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parameter HALF_TAPS = TAPS / 2; // 16 unique coefficient pairs
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parameter COEFF_WIDTH = 18;
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parameter DATA_WIDTH = 18;
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parameter ACCUM_WIDTH = 36; // legacy threshold base — DO NOT widen casually
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parameter PREADD_W = DATA_WIDTH + 1; // 19 — sum of two 18-bit signed
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parameter PROD_W = PREADD_W + COEFF_WIDTH; // 37 — pre-add * coeff
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parameter SUM_W = PROD_W + 4; // 41 — sum of 16 products
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// ============================================================================
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// Pipelined FIR filter for 100 MHz timing closure
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//
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// Problem: The original fully-combinatorial adder tree for 32 multiply products
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// created a 31-deep DSP48E1 PCOUT cascade chain taking 56.6ns (WNS = -48.325ns).
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//
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// Solution: 5-stage pipelined binary adder tree with registered outputs at
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// each level, plus BREG (coefficient register) and MREG (multiply output
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// register) stages for DSP48E1 absorption. Each stage performs at most one
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// pairwise addition (~1.7ns DSP hop), easily fitting in the 10ns clock period.
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//
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// Pipeline stages:
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// Cycle 0: data_valid → shift delay line + latch coefficients (BREG)
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// Cycle 1: Combinatorial multiply latched into mult_reg (MREG)
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// Cycle 2: 16 pairwise sums of 32 multiply results (level 0)
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// Cycle 3: 8 pairwise sums (level 1)
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// Cycle 4: 4 pairwise sums (level 2)
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// Cycle 5: 2 pairwise sums (level 3)
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// Cycle 6: 1 final sum → accumulator_reg (level 4)
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// Cycle 7: Output saturation/rounding
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//
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// Total latency: 9 cycles from data_valid to data_out_valid
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// (was 7 before BREG+MREG addition — +2 cycles for DSP48 pipelining)
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// Throughput: 1 sample per cycle (fully pipelined)
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//
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// Input rate: 100 MSPS at clk_100m (data_valid asserted EVERY cycle in
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// steady state). The CIC `_4x` decimator drops 4:1 from clk_400m → 100 M
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// pulses/s, then the cdc_adc_to_processing CDC into clk_100m emits one
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// dst_valid per dst_clk cycle (Gray-toggle handshake at matching rate).
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// A previous comment here claimed "samples arrive every ~4 cycles"; that
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// was wrong — the 4:1 ratio applies between clk_400m and clk_100m, not as
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// further sub-sampling within clk_100m.
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//
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// Implication: this 32-tap FIR's cutoff was designed for a 25 MSPS rate
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// (the post-decimation rate that "every 4 cycles" would imply). Running
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// at 100 MSPS shifts the effective cutoff 4× above that. The system's
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// existing tests pass because the 36-bit accumulator silently wraps on
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// large sustained inputs (giving lowpass-like behaviour by accident) —
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// see the build report and the open RX-NEW-3 design question. Any future
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// DSP-saving rework of this module needs a designer call on the
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// rate-vs-coefficient mismatch.
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// Coefficient ROM (symmetric low-pass — kept identical to the unfolded
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// design so production behaviour is preserved bit-for-bit at non-saturating
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// signal levels)
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// ============================================================================
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// Filter coefficients (symmetric: coeff[k] == coeff[31-k])
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reg signed [COEFF_WIDTH-1:0] coeff [0:TAPS-1];
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// Parallel delay line
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reg signed [DATA_WIDTH-1:0] delay_line [0:TAPS-1];
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// Parallel multiply results (combinatorial)
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wire signed [DATA_WIDTH+COEFF_WIDTH-1:0] mult_result [0:TAPS-1];
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// Pipelined adder tree registers
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// Level 0: 16 pairwise sums of 32 products
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reg signed [ACCUM_WIDTH-1:0] add_l0 [0:15];
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// Level 1: 8 pairwise sums
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// USE_DSP="no" forces pure additions to fabric CARRY4 chains, freeing DSP48E1
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// slices for the FFT butterfly multipliers that otherwise spill to 18-level
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// fabric carry chains causing timing violations on the XC7A50T (120 DSP budget).
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(* USE_DSP = "no" *) reg signed [ACCUM_WIDTH-1:0] add_l1 [0:7];
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// Level 2: 4 pairwise sums
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(* USE_DSP = "no" *) reg signed [ACCUM_WIDTH-1:0] add_l2 [0:3];
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// Level 3: 2 pairwise sums
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(* USE_DSP = "no" *) reg signed [ACCUM_WIDTH-1:0] add_l3 [0:1];
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// Level 4: final sum
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(* USE_DSP = "no" *) reg signed [ACCUM_WIDTH-1:0] accumulator_reg;
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// Valid pipeline: 9-stage shift register (was 7 before BREG+MREG addition)
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// [0]=BREG done, [1]=MREG done, [2]=L0 done, [3]=L1 done, [4]=L2 done,
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// [5]=L3 done, [6]=L4/accum done, [7]=output done, [8]=spare
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// The BREG and MREG stages add 2 cycles of latency.
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reg [8:0] valid_pipe;
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// Initialize coefficients
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initial begin
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// Proper low-pass filter coefficients
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coeff[ 0] = 18'sh00AD; coeff[ 1] = 18'sh00CE; coeff[ 2] = 18'sh3FD87; coeff[ 3] = 18'sh02A6;
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coeff[ 4] = 18'sh00E0; coeff[ 5] = 18'sh3F8C0; coeff[ 6] = 18'sh0A45; coeff[ 7] = 18'sh3FD82;
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coeff[ 8] = 18'sh3F0B5; coeff[ 9] = 18'sh1CAD; coeff[10] = 18'sh3EE59; coeff[11] = 18'sh3E821;
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@@ -103,226 +80,154 @@ initial begin
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end
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// ============================================================================
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// DSP48E1 PIPELINE REGISTERS (BREG + MREG)
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// Saturation thresholds — built via bit concatenation to dodge the Verilog
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// 32-bit-literal trap: writing `1 <<< 34` evaluates the `1` as a 32-bit
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// integer and silently wraps to 0, so `(1 <<< 34) - 1` becomes -1 and
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// every nonneg accumulator value would falsely saturate. The earlier
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// symmetric draft tripped this. Bit-pattern construction makes the width
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// explicit and overflow-safe.
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// ============================================================================
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// Vivado DRC warnings DPIP-1 (input not pipelined) and DPOP-2 (output not
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// pipelined) indicate that the DSP48E1 internal BREG and MREG pipeline stages
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// are not being used.
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//
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// Solution: Add explicit registered stages that Vivado can absorb into DSP48E1:
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// BREG: coeff_reg[k] — registered copy of coeff[k], feeds DSP48 B-port
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// MREG: mult_reg[k] — registered multiply output, feeds DSP48 P-port
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//
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// With these registers, Vivado sets BREG=1 and MREG=1 inside DSP48E1,
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// eliminating 68 DPIP-1 + 35 DPOP-2 warnings and improving timing.
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//
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// Pipeline impact: +2 cycles latency (BREG + MREG). Total FIR latency
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// goes from 7 to 9 cycles. Transparent relative to downstream processing
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// (Doppler/MTI operate on accumulated frames, not per-sample).
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// SAT_POS = 2^(ACCUM_WIDTH-2) - 1 = 0x3_FFFF_FFFF for ACCUM_WIDTH=36
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// SAT_NEG = -2^(ACCUM_WIDTH-2) = -0x4_0000_0000 for ACCUM_WIDTH=36
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localparam signed [SUM_W-1:0] SAT_POS = {1'b0, {(ACCUM_WIDTH-2){1'b1}}};
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localparam signed [SUM_W-1:0] SAT_NEG = -SAT_POS - 1;
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// ============================================================================
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// Registered coefficients (BREG — absorbed into DSP48E1 B-port register)
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reg signed [COEFF_WIDTH-1:0] coeff_reg [0:TAPS-1];
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// Registered multiply outputs (MREG — absorbed into DSP48E1 M-register)
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reg signed [DATA_WIDTH+COEFF_WIDTH-1:0] mult_reg [0:TAPS-1];
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// Combinatorial multiply (between BREG and MREG)
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wire signed [DATA_WIDTH+COEFF_WIDTH-1:0] mult_comb [0:TAPS-1];
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genvar k;
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generate
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for (k = 0; k < TAPS; k = k + 1) begin : mult_gen
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assign mult_comb[k] = delay_line[k] * coeff_reg[k];
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end
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endgenerate
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// mult_result now comes from the registered multiply output (MREG stage)
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genvar m;
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generate
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for (m = 0; m < TAPS; m = m + 1) begin : mult_alias
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assign mult_result[m] = mult_reg[m];
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end
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endgenerate
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// Delay line — 32 entries, shifts on data_valid (1 sample/cycle production)
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// ============================================================================
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reg signed [DATA_WIDTH-1:0] delay_line [0:TAPS-1];
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integer i;
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// ============================================================================
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// Pipeline Stage 0: Shift delay line on data_valid
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// Sync reset: enables DSP48E1 AREG/BREG absorption for delay_line registers
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// feeding the multipliers. Async reset (FDCE) prevented Vivado from using
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// the DSP48E1 internal A/B pipeline registers — the source of 2,522 DPIR-1
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// methodology warnings in Build 9. Converting to sync reset (FDRE) allows
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// Vivado to absorb these into DSP48E1 AREG/BREG, further reducing LUT count.
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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delay_line[i] <= 0;
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end
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for (i = 0; i < TAPS; i = i + 1) delay_line[i] <= 0;
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end else if (data_valid) begin
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for (i = TAPS-1; i > 0; i = i - 1) begin
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delay_line[i] <= delay_line[i-1];
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end
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for (i = TAPS-1; i > 0; i = i - 1) delay_line[i] <= delay_line[i-1];
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delay_line[0] <= data_in;
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end
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end
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// ============================================================================
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// Pipeline Stage 0b (BREG): Register coefficients
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// Runs on data_valid alongside delay_line shift.
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// Vivado absorbs into DSP48E1 B-port pipeline register (BREG=1).
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// Stage 1 (DREG/AREG): pre-adder operands + coefficient register.
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// Vivado absorbs into DSP48E1 D and A pre-adder ports + B coefficient port.
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// ============================================================================
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reg signed [DATA_WIDTH-1:0] pair_a [0:HALF_TAPS-1]; // delay_line[k]
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reg signed [DATA_WIDTH-1:0] pair_d [0:HALF_TAPS-1]; // delay_line[31-k]
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reg signed [COEFF_WIDTH-1:0] coeff_reg [0:HALF_TAPS-1];
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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for (i = 0; i < HALF_TAPS; i = i + 1) begin
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pair_a[i] <= 0;
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pair_d[i] <= 0;
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coeff_reg[i] <= 0;
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end
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end else if (data_valid) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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for (i = 0; i < HALF_TAPS; i = i + 1) begin
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pair_a[i] <= delay_line[i];
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pair_d[i] <= delay_line[(TAPS-1) - i];
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coeff_reg[i] <= coeff[i];
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end
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end
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end
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// ============================================================================
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// Pipeline Stage 0c (MREG): Register multiply outputs
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// Captures combinatorial multiply results one cycle after BREG.
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// Vivado absorbs into DSP48E1 M-register (MREG=1).
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// Stage 2 (MREG): pre-add + multiply. Vivado infers DSP48E1 P = (D+A)*B.
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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mult_reg[i] <= 0;
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end
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end else if (valid_pipe[0]) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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mult_reg[i] <= mult_comb[i];
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reg signed [PROD_W-1:0] mult_reg [0:HALF_TAPS-1];
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reg [10:0] valid_pipe; // 11-stage pipeline tracker
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genvar gk;
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generate
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for (gk = 0; gk < HALF_TAPS; gk = gk + 1) begin : mac_gen
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wire signed [PREADD_W-1:0] preadd =
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$signed({pair_d[gk][DATA_WIDTH-1], pair_d[gk]}) +
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$signed({pair_a[gk][DATA_WIDTH-1], pair_a[gk]});
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always @(posedge clk) begin
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if (!reset_n)
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mult_reg[gk] <= 0;
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else if (valid_pipe[0])
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mult_reg[gk] <= preadd * coeff_reg[gk];
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end
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end
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end
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endgenerate
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// ============================================================================
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// Pipeline Stage 1 (Level 0): Register 16 pairwise sums of 32 multiply results
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// Each addition is a single 36-bit add — one DSP48E1 hop (~1.7ns), fits 10ns.
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// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
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// Now uses mult_result (from mult_reg/MREG stage) instead of combinatorial multiply.
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// Adder tree: 16 → 8 → 4 → 2 → 1 (4 stages, fabric carry chains).
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// Intermediates widened so the 37-bit pre-add products grow without
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// silent wrap (sum-of-16 worst case = 37 + 4 = 41 bits).
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// ============================================================================
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(* USE_DSP = "no" *) reg signed [PROD_W:0] add_l0 [0:7]; // 38-bit
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(* USE_DSP = "no" *) reg signed [PROD_W+1:0] add_l1 [0:3]; // 39-bit
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(* USE_DSP = "no" *) reg signed [PROD_W+2:0] add_l2 [0:1]; // 40-bit
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(* USE_DSP = "no" *) reg signed [SUM_W-1:0] accumulator_reg; // 41-bit
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < 16; i = i + 1) begin
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add_l0[i] <= 0;
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end
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for (i = 0; i < 8; i = i + 1) add_l0[i] <= 0;
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end else if (valid_pipe[1]) begin
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for (i = 0; i < 16; i = i + 1) begin
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// mult_result is (DATA_WIDTH + COEFF_WIDTH) = 36 bits = ACCUM_WIDTH,
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// so no sign extension is needed. Direct assignment preserves the
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// signed multiply result. (Fixes Vivado Synth 8-693 "zero replication
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// count" warning from the original {0{sign_bit}} expression.)
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add_l0[i] <= mult_result[2*i] + mult_result[2*i+1];
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end
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for (i = 0; i < 8; i = i + 1)
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add_l0[i] <= $signed(mult_reg[2*i]) + $signed(mult_reg[2*i+1]);
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end
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end
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// ============================================================================
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// Pipeline Stage 2 (Level 1): 8 pairwise sums of 16 Level-0 results
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// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < 8; i = i + 1) begin
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add_l1[i] <= 0;
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end
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for (i = 0; i < 4; i = i + 1) add_l1[i] <= 0;
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end else if (valid_pipe[2]) begin
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for (i = 0; i < 8; i = i + 1) begin
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add_l1[i] <= add_l0[2*i] + add_l0[2*i+1];
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end
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for (i = 0; i < 4; i = i + 1)
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add_l1[i] <= $signed(add_l0[2*i]) + $signed(add_l0[2*i+1]);
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end
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end
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// ============================================================================
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// Pipeline Stage 3 (Level 2): 4 pairwise sums of 8 Level-1 results
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// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < 4; i = i + 1) begin
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add_l2[i] <= 0;
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end
|
||||
add_l2[0] <= 0;
|
||||
add_l2[1] <= 0;
|
||||
end else if (valid_pipe[3]) begin
|
||||
for (i = 0; i < 4; i = i + 1) begin
|
||||
add_l2[i] <= add_l1[2*i] + add_l1[2*i+1];
|
||||
end
|
||||
add_l2[0] <= $signed(add_l1[0]) + $signed(add_l1[1]);
|
||||
add_l2[1] <= $signed(add_l1[2]) + $signed(add_l1[3]);
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Pipeline Stage 4 (Level 3): 2 pairwise sums of 4 Level-2 results
|
||||
// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
|
||||
// ============================================================================
|
||||
always @(posedge clk) begin
|
||||
if (!reset_n) begin
|
||||
add_l3[0] <= 0;
|
||||
add_l3[1] <= 0;
|
||||
end else if (valid_pipe[4]) begin
|
||||
add_l3[0] <= add_l2[0] + add_l2[1];
|
||||
add_l3[1] <= add_l2[2] + add_l2[3];
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Pipeline Stage 5 (Level 4): Final sum of 2 Level-3 results
|
||||
// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
|
||||
// ============================================================================
|
||||
always @(posedge clk) begin
|
||||
if (!reset_n) begin
|
||||
if (!reset_n)
|
||||
accumulator_reg <= 0;
|
||||
end else if (valid_pipe[5]) begin
|
||||
accumulator_reg <= add_l3[0] + add_l3[1];
|
||||
end
|
||||
else if (valid_pipe[4])
|
||||
accumulator_reg <= $signed(add_l2[0]) + $signed(add_l2[1]);
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Pipeline Stage 6: Output saturation/rounding (registered)
|
||||
// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
|
||||
// Output saturation — same thresholds and bit-slice as the unfolded design
|
||||
// ============================================================================
|
||||
always @(posedge clk) begin
|
||||
if (!reset_n) begin
|
||||
data_out <= 0;
|
||||
data_out_valid <= 0;
|
||||
data_out <= 0;
|
||||
data_out_valid <= 1'b0;
|
||||
end else begin
|
||||
data_out_valid <= valid_pipe[6];
|
||||
|
||||
if (valid_pipe[6]) begin
|
||||
// Output saturation logic
|
||||
if (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) begin
|
||||
data_out <= (2**(DATA_WIDTH-1))-1;
|
||||
end else if (accumulator_reg < -(2**(ACCUM_WIDTH-2))) begin
|
||||
data_out <= -(2**(DATA_WIDTH-1));
|
||||
end else begin
|
||||
// Round and truncate (keep middle bits)
|
||||
data_out_valid <= valid_pipe[5];
|
||||
if (valid_pipe[5]) begin
|
||||
if (accumulator_reg > SAT_POS)
|
||||
data_out <= {1'b0, {(DATA_WIDTH-1){1'b1}}}; // +max
|
||||
else if (accumulator_reg < SAT_NEG)
|
||||
data_out <= {1'b1, {(DATA_WIDTH-1){1'b0}}}; // -max
|
||||
else
|
||||
data_out <= accumulator_reg[ACCUM_WIDTH-2:DATA_WIDTH-1];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// Valid pipeline shift register (9-stage for BREG+MREG+5-level adder+output)
|
||||
// Sync reset — no DSP48 involvement but keeps reset style consistent with datapath
|
||||
// Valid pipeline (11 stages: shift+pair → MREG → 4 adder levels → output)
|
||||
// ============================================================================
|
||||
always @(posedge clk) begin
|
||||
if (!reset_n) begin
|
||||
valid_pipe <= 9'b000000000;
|
||||
end else begin
|
||||
valid_pipe <= {valid_pipe[7:0], data_valid};
|
||||
end
|
||||
if (!reset_n) valid_pipe <= 11'd0;
|
||||
else valid_pipe <= {valid_pipe[9:0], data_valid};
|
||||
end
|
||||
|
||||
// Always ready to accept new data (fully pipelined)
|
||||
assign fir_ready = 1'b1;
|
||||
assign fir_ready = 1'b1; // always ready — fully pipelined at 1 sample/cycle
|
||||
|
||||
// Overflow detection
|
||||
assign filter_overflow = (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) ||
|
||||
(accumulator_reg < -(2**(ACCUM_WIDTH-2)));
|
||||
assign filter_overflow =
|
||||
(accumulator_reg > SAT_POS) || (accumulator_reg < SAT_NEG);
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user