mirror of
https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-09 06:57:15 +00:00
chore: delete dead latency_buffer; doc cleanup for two stale comments
latency_buffer.v has had zero non-tb instantiations since RX-B (2026-04-23)
replaced its hookup in radar_receiver_final with a 1-FF alignment register.
The module was being kept "for potential future use" — exactly the kind of
dead weight the codebase does not need. Deleted, along with all build /
test infrastructure that dragged it along:
- 9_Firmware/9_2_FPGA/latency_buffer.v
- 9_Firmware/9_2_FPGA/tb/tb_latency_buffer.v
- run_regression.sh: removed from RTL_FILES and RECEIVER_RTL
- scripts/200t/build_200t.tcl: removed from synthesis source list
- tb/tb_system_e2e.v: removed from header compile-string example
- tb/cosim/validate_mem_files.py: deleted test_latency_buffer() (~75 lines),
its call site, and the corresponding entry in the module docstring
Historical RX-B comments referencing latency_buffer in radar_receiver_final.v,
tb_rxb_fullchain_latency.v, and tb_rxb_latency_measure.v are kept — they
explain WHY the module was removed, which is still useful design archaeology.
Two doc-only housekeeping touches bundled in:
- plfm_chirp_controller.v: replaced two empty "CRITICAL FIX: Generate
valid signal" labels at LONG_CHIRP and SHORT_CHIRP with one shared
chirp_valid policy comment block above LONG_CHIRP that explains the
actual rationale (downstream FIFO underrun on trailing samples).
- v7/models.py: replaced the "range_resolution and velocity_resolution
should be calibrated" docstring (sounded like an open TODO but was a
documented placeholder) with a clear pointer to the GUI-C3 fix in
workers.py:RadarDataWorker so future readers know the live path
derives correct values from WaveformConfig.
FPGA quick regression unchanged: 28/29 (1 fail is the unrelated iverilog/
Xilinx-IP RX-NEW-3 gap). GUI suite 180/180. Ruff clean.
This commit is contained in:
Jason
@@ -1,131 +0,0 @@
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`timescale 1ns / 1ps
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// latency_buffer.v — Parameterized BRAM-based latency/delay buffer
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// Renamed from latency_buffer_2159 to latency_buffer (module name was
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// inconsistent with the actual LATENCY=3187 parameter).
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module latency_buffer #(
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parameter DATA_WIDTH = 32,
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parameter LATENCY = 3187
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) (
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input wire clk,
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input wire reset_n,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire valid_in,
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output wire [DATA_WIDTH-1:0] data_out,
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output wire valid_out
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);
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// ========== FIXED PARAMETERS ==========
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localparam ADDR_WIDTH = 12; // Enough for 4096 entries (>2159)
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// ========== FIXED LOGIC ==========
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(* ram_style = "block" *) reg [DATA_WIDTH-1:0] bram [0:4095];
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reg [ADDR_WIDTH-1:0] write_ptr;
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reg [ADDR_WIDTH-1:0] read_ptr;
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reg valid_out_reg;
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// Delay counter to track when LATENCY cycles have passed
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reg [ADDR_WIDTH-1:0] delay_counter;
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reg buffer_has_data; // Flag when buffer has accumulated LATENCY samples
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// ========== FIXED INITIALIZATION ==========
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integer k;
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initial begin
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for (k = 0; k < 4096; k = k + 1) begin
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bram[k] = {DATA_WIDTH{1'b0}};
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end
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write_ptr = 0;
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read_ptr = 0;
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valid_out_reg = 0;
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delay_counter = 0;
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buffer_has_data = 0;
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end
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// ========== BRAM WRITE (synchronous only, no async reset) ==========
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// Xilinx Block RAMs do not support asynchronous resets.
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// Separating the BRAM write into its own always block avoids Synth 8-3391.
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// The initial block above handles power-on initialization for FPGA.
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always @(posedge clk) begin
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if (valid_in) begin
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bram[write_ptr] <= data_in;
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end
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end
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// ========== CONTROL LOGIC (with async reset) ==========
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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write_ptr <= 0;
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read_ptr <= 0;
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valid_out_reg <= 0;
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delay_counter <= 0;
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buffer_has_data <= 0;
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end else begin
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// Default: no valid output
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valid_out_reg <= 0;
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// ===== WRITE SIDE =====
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if (valid_in) begin
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// Increment write pointer (wrap at 4095)
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if (write_ptr == 4095) begin
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write_ptr <= 0;
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end else begin
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write_ptr <= write_ptr + 1;
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end
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// Count how many samples we've written
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if (delay_counter < LATENCY) begin
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delay_counter <= delay_counter + 1;
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// When we've written LATENCY samples, buffer is "primed"
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if (delay_counter == LATENCY - 1) begin
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buffer_has_data <= 1'b1;
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end
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end
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end
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// ===== READ SIDE =====
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// Only start reading after we have LATENCY samples in buffer
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if (buffer_has_data && valid_in) begin
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// Read pointer follows write pointer with LATENCY delay
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// Calculate: read_ptr = (write_ptr - LATENCY) mod 4096
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// Handle wrap-around correctly
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if (write_ptr >= LATENCY) begin
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read_ptr <= write_ptr - LATENCY;
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end else begin
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// Wrap around: 4096 + write_ptr - LATENCY
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read_ptr <= 4096 + write_ptr - LATENCY;
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end
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// Output is valid
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valid_out_reg <= 1'b1;
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end
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end
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end
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// ========== BRAM READ (synchronous — required for Block RAM inference) ==========
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// Xilinx Block RAMs physically register the read output. An async read
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// (assign data_out = bram[addr]) forces Vivado to use distributed LUTRAM
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// instead, wasting ~704 LUTs. Registering the read adds 1 cycle of latency,
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// compensated by the valid pipeline stage below.
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reg [DATA_WIDTH-1:0] data_out_reg;
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always @(posedge clk) begin
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data_out_reg <= bram[read_ptr];
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end
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// Pipeline valid_out_reg by 1 cycle to align with registered BRAM read
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reg valid_out_pipe;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n)
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valid_out_pipe <= 1'b0;
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else
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valid_out_pipe <= valid_out_reg;
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end
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assign data_out = data_out_reg;
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assign valid_out = valid_out_pipe;
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endmodule
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@@ -280,11 +280,16 @@ always @(posedge clk_120m or negedge reset_n) begin
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chirp_data <= 8'd128;
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end
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// chirp_valid policy (LONG_CHIRP + SHORT_CHIRP states): assert
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// chirp_valid HIGH for the entire active-sample window of each
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// chirp (sample_counter < T?_SAMPLES) so the downstream DAC sees a
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// continuous data-valid pulse, then ride out the remaining state
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// duration on idle code 8'd128. Without the per-cycle assert,
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// downstream FIFOs underrun on the trailing samples of each chirp.
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LONG_CHIRP: begin
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rf_switch_ctrl <= 1'b1;
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{adar_tr_1, adar_tr_2, adar_tr_3, adar_tr_4} <= 4'b1111;
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// CRITICAL FIX: Generate valid signal
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if (sample_counter < T1_SAMPLES) begin
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chirp_data <= long_chirp_rd_data;
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chirp_valid <= 1'b1; // Valid during entire chirp
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@@ -306,8 +311,8 @@ always @(posedge clk_120m or negedge reset_n) begin
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SHORT_CHIRP: begin
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rf_switch_ctrl <= 1'b1;
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{adar_tr_1, adar_tr_2, adar_tr_3, adar_tr_4} <= 4'b1111;
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// CRITICAL FIX: Generate valid signal for short chirp
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/* see chirp_valid policy block above LONG_CHIRP */
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if (sample_counter < T2_SAMPLES) begin
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chirp_data <= short_chirp_lut[sample_counter];
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chirp_valid <= 1'b1; // Valid during entire chirp
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@@ -62,7 +62,6 @@ PROD_RTL=(
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fir_lowpass.v
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ddc_input_interface.v
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chirp_memory_loader_param.v
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latency_buffer.v
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matched_filter_multi_segment.v
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matched_filter_processing_chain.v
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range_bin_decimator.v
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@@ -101,7 +100,7 @@ RECEIVER_RTL=(
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tb/ad9484_interface_400m_stub.v
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ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v
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cdc_modules.v fir_lowpass.v ddc_input_interface.v
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chirp_memory_loader_param.v latency_buffer.v
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chirp_memory_loader_param.v
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matched_filter_multi_segment.v matched_filter_processing_chain.v
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range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
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xfft_2048.v fft_engine_axi_bridge.v
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@@ -64,7 +64,6 @@ set rtl_files [list \
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"${rtl_dir}/edge_detector.v" \
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"${rtl_dir}/fir_lowpass.v" \
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"${rtl_dir}/frequency_matched_filter.v" \
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"${rtl_dir}/latency_buffer.v" \
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"${rtl_dir}/matched_filter_multi_segment.v" \
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"${rtl_dir}/matched_filter_processing_chain.v" \
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"${rtl_dir}/nco_400m_enhanced.v" \
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@@ -7,7 +7,6 @@ Checks:
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2. FFT twiddle files: bit-exact match against cos(2*pi*k/N) in Q15
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3. Long chirp .mem files: reverse-engineer parameters, check for chirp structure
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4. Short chirp .mem files: check length, value range, spectral content
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5. latency_buffer LATENCY=3187 parameter validation
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Usage:
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python3 validate_mem_files.py
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@@ -378,81 +377,6 @@ def test_chirp_vs_model():
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)
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# ============================================================================
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# TEST 6: Latency Buffer LATENCY=3187 Validation
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# ============================================================================
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def test_latency_buffer():
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# The latency buffer delays the reference chirp data to align with
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# the matched filter processing chain output.
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#
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# The total latency through the processing chain depends on the branch:
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#
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# SYNTHESIS branch (fft_engine.v):
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# - Load: 1024 cycles (input)
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# - Forward FFT: LOG2N=10 stages x N/2=512 butterflies x 5-cycle pipeline = variable
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# - Reference FFT: same
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# - Conjugate multiply: 1024 cycles (4-stage pipeline in frequency_matched_filter)
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# - Inverse FFT: same as forward
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# - Output: 1024 cycles
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# Total: roughly 3000-4000 cycles depending on pipeline fill
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#
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# The LATENCY=3187 value was likely determined empirically to align
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# the reference chirp arriving at the processing chain with the
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# correct time-domain position.
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#
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# Key constraint: LATENCY must be < 4096 (BRAM buffer size)
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LATENCY = 3187
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BRAM_SIZE = 4096
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check(LATENCY < BRAM_SIZE,
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f"LATENCY ({LATENCY}) < BRAM size ({BRAM_SIZE})")
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# The fft_engine processes in stages:
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# - LOAD: 1024 clocks (accepts input)
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# - Per butterfly stage: 512 butterflies x 5 pipeline stages = ~2560 clocks + overhead
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# Actually: 512 butterflies, each takes 5 cycles = 2560 per stage, 10 stages
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# Total compute: 10 * 2560 = 25600 clocks
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# But this is just for ONE FFT. The chain does 3 FFTs + multiply.
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#
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# For the SIMULATION branch, it's 1 clock per operation (behavioral).
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# LATENCY=3187 doesn't apply to simulation branch behavior —
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# it's the physical hardware pipeline latency.
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#
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# For synthesis: the latency_buffer feeds ref data to the chain via
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# chirp_memory_loader_param → latency_buffer → chain.
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# But wait — looking at radar_receiver_final.v:
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# - mem_request drives valid_in on the latency buffer
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# - The buffer delays {ref_i, ref_q} by LATENCY valid_in cycles
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# - The delayed output feeds long_chirp_real/imag → chain
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#
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# The purpose: the chain in the SYNTHESIS branch reads reference data
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# via the long_chirp_real/imag ports DURING ST_FWD_FFT (while collecting
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# input samples). The reference data needs to arrive LATENCY cycles
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# after the first mem_request, where LATENCY accounts for:
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# - The fft_engine pipeline latency from input to output
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# - Specifically, the chain processes: load 1024 → FFT → FFT → multiply → IFFT → output
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# The reference is consumed during the second FFT (ST_REF_BITREV/BUTTERFLY)
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# which starts after the first FFT completes.
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# For now, validate that LATENCY is reasonable (between 1000 and 4095)
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check(1000 < LATENCY < 4095,
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f"LATENCY={LATENCY} in reasonable range [1000, 4095]")
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# Check that the module name vs parameter is consistent
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# Module name was renamed from latency_buffer_2159 to latency_buffer
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# to match the actual parameterized LATENCY value. No warning needed.
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# Validate address arithmetic won't overflow
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min_read_ptr = 4096 + 0 - LATENCY
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check(min_read_ptr >= 0 and min_read_ptr < 4096,
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f"Min read_ptr after wrap = {min_read_ptr} (valid: 0..4095)")
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# The latency buffer uses valid_in gated reads, so it only counts
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# valid samples. The number of valid_in pulses between first write
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# and first read is LATENCY.
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# ============================================================================
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# TEST 7: Cross-check chirp memory loader addressing
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# ============================================================================
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@@ -553,7 +477,6 @@ def main():
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test_long_chirp()
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test_short_chirp()
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test_chirp_vs_model()
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test_latency_buffer()
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test_memory_addressing()
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test_seg3_padding()
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@@ -1,398 +0,0 @@
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`timescale 1ns / 1ps
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module tb_latency_buffer;
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// ── Parameters ─────────────────────────────────────────────
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localparam CLK_PERIOD = 10.0; // 100 MHz
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localparam DATA_WIDTH = 32;
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// Use small LATENCY for fast simulation; full 3187 is too slow for iverilog
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localparam LATENCY = 17;
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// ── Signals ────────────────────────────────────────────────
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reg clk;
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reg reset_n;
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reg [DATA_WIDTH-1:0] data_in;
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reg valid_in;
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wire [DATA_WIDTH-1:0] data_out;
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wire valid_out;
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// ── Test bookkeeping ───────────────────────────────────────
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integer pass_count;
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integer fail_count;
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integer test_num;
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integer i;
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reg [DATA_WIDTH-1:0] expected;
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integer valid_output_count;
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integer first_valid_cycle;
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reg saw_valid;
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// ── Clock ──────────────────────────────────────────────────
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always #(CLK_PERIOD/2) clk = ~clk;
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// ── DUT ────────────────────────────────────────────────────
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latency_buffer #(
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.DATA_WIDTH(DATA_WIDTH),
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.LATENCY(LATENCY)
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) uut (
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.clk (clk),
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.reset_n (reset_n),
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.data_in (data_in),
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.valid_in (valid_in),
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.data_out (data_out),
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.valid_out(valid_out)
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);
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// ── Check task ─────────────────────────────────────────────
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task check;
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input cond;
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input [511:0] label;
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begin
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test_num = test_num + 1;
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if (cond) begin
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$display("[PASS] Test %0d: %0s", test_num, label);
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pass_count = pass_count + 1;
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end else begin
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$display("[FAIL] Test %0d: %0s", test_num, label);
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fail_count = fail_count + 1;
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end
|
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end
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endtask
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// ── Helper: apply reset ────────────────────────────────────
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task do_reset;
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begin
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reset_n = 0;
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valid_in = 0;
|
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data_in = 0;
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repeat (4) @(posedge clk);
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reset_n = 1;
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@(posedge clk); #1;
|
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end
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endtask
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|
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// ── Stimulus ───────────────────────────────────────────────
|
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initial begin
|
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$dumpfile("tb_latency_buffer.vcd");
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$dumpvars(0, tb_latency_buffer);
|
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|
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clk = 0;
|
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reset_n = 0;
|
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data_in = 0;
|
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valid_in = 0;
|
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pass_count = 0;
|
||||
fail_count = 0;
|
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test_num = 0;
|
||||
|
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// ════════════════════════════════════════════════════════
|
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// TEST GROUP 1: Reset behaviour
|
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// ════════════════════════════════════════════════════════
|
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$display("\n--- Test Group 1: Reset Behaviour ---");
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repeat (4) @(posedge clk); #1;
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check(valid_out === 1'b0, "valid_out = 0 during reset");
|
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check(data_out === {DATA_WIDTH{1'b0}}, "data_out = 0 during reset");
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
// TEST GROUP 2: Priming phase — no output for LATENCY cycles
|
||||
// ════════════════════════════════════════════════════════
|
||||
$display("\n--- Test Group 2: Priming Phase ---");
|
||||
do_reset;
|
||||
|
||||
// Feed samples 1, 2, 3, ... continuously
|
||||
saw_valid = 0;
|
||||
for (i = 0; i < LATENCY; i = i + 1) begin
|
||||
data_in = i + 1;
|
||||
valid_in = 1;
|
||||
@(posedge clk); #1;
|
||||
if (valid_out) saw_valid = 1;
|
||||
end
|
||||
check(!saw_valid, "No valid output during first LATENCY input samples");
|
||||
|
||||
// The LATENCY-th sample is being written THIS cycle.
|
||||
// The buffer_has_data flag is set when delay_counter == LATENCY-1,
|
||||
// which happens on the LATENCY-th valid_in pulse (i == LATENCY-1 above).
|
||||
// But valid_out only appears on the NEXT valid_in cycle because
|
||||
// buffer_has_data is registered.
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
// TEST GROUP 3: Exact latency measurement
|
||||
// ════════════════════════════════════════════════════════
|
||||
$display("\n--- Test Group 3: Exact Latency Measurement ---");
|
||||
do_reset;
|
||||
|
||||
// Feed a known sequence: sample N has value (N+1)
|
||||
// After priming, output[N] should equal input[N - LATENCY]
|
||||
valid_output_count = 0;
|
||||
first_valid_cycle = -1;
|
||||
|
||||
for (i = 0; i < LATENCY + 20; i = i + 1) begin
|
||||
data_in = i + 1;
|
||||
valid_in = 1;
|
||||
@(posedge clk); #1;
|
||||
if (valid_out) begin
|
||||
if (first_valid_cycle < 0) first_valid_cycle = i;
|
||||
valid_output_count = valid_output_count + 1;
|
||||
end
|
||||
end
|
||||
|
||||
$display(" First valid output at input sample #%0d (expected ~%0d)",
|
||||
first_valid_cycle, LATENCY + 1);
|
||||
// After LATENCY samples written, buffer_has_data goes high.
|
||||
// On the NEXT valid_in, valid_out_reg fires. Then valid_out_pipe
|
||||
// (the actual output) fires one cycle later due to BRAM read register.
|
||||
// So first valid is at sample LATENCY + 1.
|
||||
check(first_valid_cycle == LATENCY + 1,
|
||||
"First valid output appears at sample LATENCY+1 (BRAM read pipeline)");
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
// TEST GROUP 4: Data integrity (exact delay)
|
||||
// ════════════════════════════════════════════════════════
|
||||
$display("\n--- Test Group 4: Data Integrity ---");
|
||||
do_reset;
|
||||
|
||||
// Feed samples: value = (i + 100)
|
||||
// After priming, each valid output should match data_in from LATENCY samples ago.
|
||||
//
|
||||
// The DUT calculates read_ptr from write_ptr, with BRAM read output
|
||||
// registered for Block RAM inference. This adds 1 cycle of read latency
|
||||
// beyond the LATENCY parameter. The valid_out pipeline stage tracks this.
|
||||
// The auto-calibration below handles any offset empirically.
|
||||
|
||||
begin : data_check_block
|
||||
reg all_match;
|
||||
reg [DATA_WIDTH-1:0] input_history [0:4095];
|
||||
integer out_idx;
|
||||
integer match_count;
|
||||
integer expected_idx;
|
||||
|
||||
all_match = 1;
|
||||
match_count = 0;
|
||||
out_idx = 0;
|
||||
|
||||
for (i = 0; i < LATENCY + 100; i = i + 1) begin
|
||||
data_in = i + 100;
|
||||
input_history[i] = i + 100;
|
||||
valid_in = 1;
|
||||
@(posedge clk); #1;
|
||||
if (valid_out) begin
|
||||
// Determine which input this output corresponds to.
|
||||
// The first valid output appears at input cycle LATENCY.
|
||||
// At that point, read_ptr was set from write_ptr = LATENCY
|
||||
// => read_ptr = LATENCY - LATENCY = 0 => bram[0] = input_history[0].
|
||||
// But read_ptr is registered, so it takes effect next cycle.
|
||||
// Actually, let's just check: output should be input_history[out_idx]
|
||||
// where out_idx starts from 0.
|
||||
expected = input_history[out_idx];
|
||||
if (data_out !== expected) begin
|
||||
// Try out_idx+1 (off-by-one from registered read_ptr)
|
||||
if (out_idx > 0 && data_out === input_history[out_idx - 1]) begin
|
||||
// off by one — adjust
|
||||
end else begin
|
||||
if (all_match && match_count == 0) begin
|
||||
// First output — calibrate
|
||||
// Find which index data_out matches
|
||||
begin : find_idx
|
||||
integer j;
|
||||
for (j = 0; j <= i; j = j + 1) begin
|
||||
if (input_history[j] === data_out) begin
|
||||
out_idx = j;
|
||||
disable find_idx;
|
||||
end
|
||||
end
|
||||
// No match found
|
||||
all_match = 0;
|
||||
$display(" [WARN] First output %0d does not match any input",
|
||||
data_out);
|
||||
end
|
||||
end else begin
|
||||
all_match = 0;
|
||||
$display(" [WARN] Mismatch at out#%0d: got %0d, exp %0d",
|
||||
match_count, data_out, expected);
|
||||
end
|
||||
end
|
||||
end
|
||||
match_count = match_count + 1;
|
||||
out_idx = out_idx + 1;
|
||||
end
|
||||
end
|
||||
|
||||
$display(" Verified %0d output samples", match_count);
|
||||
check(match_count > 0, "Produced output samples after priming");
|
||||
check(all_match, "All outputs match input delayed by LATENCY");
|
||||
end
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
// TEST GROUP 5: Valid gating — no output when valid_in=0
|
||||
// ════════════════════════════════════════════════════════
|
||||
$display("\n--- Test Group 5: Valid Gating ---");
|
||||
do_reset;
|
||||
|
||||
// Prime the buffer
|
||||
for (i = 0; i < LATENCY + 5; i = i + 1) begin
|
||||
data_in = i + 1;
|
||||
valid_in = 1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
|
||||
// Now de-assert valid_in — after pipeline drains (1 cycle), no more outputs
|
||||
valid_in = 0;
|
||||
data_in = 32'hDEADBEEF;
|
||||
// Allow 1 cycle for the valid pipeline to drain
|
||||
@(posedge clk); #1;
|
||||
valid_output_count = 0;
|
||||
for (i = 0; i < 20; i = i + 1) begin
|
||||
@(posedge clk); #1;
|
||||
if (valid_out) valid_output_count = valid_output_count + 1;
|
||||
end
|
||||
check(valid_output_count == 0, "No output when valid_in deasserted (after pipeline drain)");
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
// TEST GROUP 6: Intermittent valid_in
|
||||
// ════════════════════════════════════════════════════════
|
||||
$display("\n--- Test Group 6: Intermittent Valid ---");
|
||||
do_reset;
|
||||
|
||||
// Feed with valid_in toggling every other cycle
|
||||
valid_output_count = 0;
|
||||
begin : intermittent_block
|
||||
integer valid_in_count;
|
||||
valid_in_count = 0;
|
||||
|
||||
for (i = 0; i < (LATENCY + 30) * 2; i = i + 1) begin
|
||||
if (i[0] == 1'b0) begin
|
||||
data_in = valid_in_count + 200;
|
||||
valid_in = 1;
|
||||
valid_in_count = valid_in_count + 1;
|
||||
end else begin
|
||||
valid_in = 0;
|
||||
end
|
||||
@(posedge clk); #1;
|
||||
if (valid_out) valid_output_count = valid_output_count + 1;
|
||||
end
|
||||
end
|
||||
|
||||
$display(" Intermittent: %0d valid outputs", valid_output_count);
|
||||
check(valid_output_count > 0, "Outputs produced with intermittent valid_in");
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
// TEST GROUP 7: Pointer wrap-around
|
||||
// ════════════════════════════════════════════════════════
|
||||
$display("\n--- Test Group 7: Pointer Wrap-Around ---");
|
||||
do_reset;
|
||||
|
||||
// Feed 4096 + LATENCY + 50 samples to force write_ptr wrap-around
|
||||
// (4096 is the BRAM depth)
|
||||
begin : wrap_block
|
||||
reg wrap_all_match;
|
||||
reg [DATA_WIDTH-1:0] wrap_history [0:8191];
|
||||
integer wrap_out_idx;
|
||||
integer wrap_match_count;
|
||||
integer total_samples;
|
||||
|
||||
total_samples = 4096 + LATENCY + 50;
|
||||
wrap_all_match = 1;
|
||||
wrap_match_count = 0;
|
||||
wrap_out_idx = 0;
|
||||
|
||||
for (i = 0; i < total_samples; i = i + 1) begin
|
||||
data_in = i + 500;
|
||||
wrap_history[i] = i + 500;
|
||||
valid_in = 1;
|
||||
@(posedge clk); #1;
|
||||
if (valid_out) begin
|
||||
if (wrap_match_count == 0) begin
|
||||
// Calibrate: find which index
|
||||
begin : find_wrap_idx
|
||||
integer j;
|
||||
for (j = 0; j <= i; j = j + 1) begin
|
||||
if (wrap_history[j] === data_out) begin
|
||||
wrap_out_idx = j;
|
||||
disable find_wrap_idx;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
expected = wrap_history[wrap_out_idx];
|
||||
if (data_out !== expected) begin
|
||||
wrap_all_match = 0;
|
||||
if (wrap_match_count < 5) begin
|
||||
$display(" [WARN] Wrap mismatch out#%0d: got %0d, exp %0d",
|
||||
wrap_match_count, data_out, expected);
|
||||
end
|
||||
end
|
||||
end
|
||||
wrap_match_count = wrap_match_count + 1;
|
||||
wrap_out_idx = wrap_out_idx + 1;
|
||||
end
|
||||
end
|
||||
|
||||
$display(" Wrap-around: %0d outputs verified", wrap_match_count);
|
||||
check(wrap_match_count > 4096, "More than 4096 outputs (proves wrap-around)");
|
||||
check(wrap_all_match, "Data integrity across pointer wrap-around");
|
||||
end
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
// TEST GROUP 8: Reset mid-operation
|
||||
// ════════════════════════════════════════════════════════
|
||||
$display("\n--- Test Group 8: Reset Mid-Operation ---");
|
||||
|
||||
// Prime and get some outputs flowing
|
||||
do_reset;
|
||||
for (i = 0; i < LATENCY + 10; i = i + 1) begin
|
||||
data_in = i + 1;
|
||||
valid_in = 1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
// Feed one more cycle to ensure pipeline has flushed
|
||||
data_in = 32'hFFFF;
|
||||
valid_in = 1;
|
||||
@(posedge clk); #1;
|
||||
// Should be producing outputs now
|
||||
check(valid_out === 1'b1, "Outputs flowing before mid-op reset");
|
||||
|
||||
// Apply reset mid-stream
|
||||
reset_n = 0;
|
||||
valid_in = 0;
|
||||
repeat (4) @(posedge clk); #1;
|
||||
check(valid_out === 1'b0, "valid_out = 0 after mid-operation reset");
|
||||
|
||||
// Release reset and verify buffer needs full re-priming
|
||||
reset_n = 1;
|
||||
@(posedge clk); #1;
|
||||
|
||||
saw_valid = 0;
|
||||
for (i = 0; i < LATENCY; i = i + 1) begin
|
||||
data_in = i + 1000;
|
||||
valid_in = 1;
|
||||
@(posedge clk); #1;
|
||||
if (valid_out) saw_valid = 1;
|
||||
end
|
||||
check(!saw_valid, "No output during re-priming after reset");
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
// TEST GROUP 9: Large LATENCY parameter test
|
||||
// ════════════════════════════════════════════════════════
|
||||
// (We use a second instance with LATENCY=100 to verify parameterization)
|
||||
// Skipped in this TB to keep simulation short — the wrap-around test
|
||||
// already validates 4000+ samples.
|
||||
|
||||
// ════════════════════════════════════════════════════════
|
||||
// Summary
|
||||
// ════════════════════════════════════════════════════════
|
||||
$display("");
|
||||
$display("========================================");
|
||||
$display(" LATENCY BUFFER TESTBENCH RESULTS");
|
||||
$display(" PASSED: %0d / %0d", pass_count, test_num);
|
||||
$display(" FAILED: %0d / %0d", fail_count, test_num);
|
||||
if (fail_count == 0)
|
||||
$display(" ** ALL TESTS PASSED **");
|
||||
else
|
||||
$display(" ** SOME TESTS FAILED **");
|
||||
$display("========================================");
|
||||
$display("");
|
||||
|
||||
#100;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -32,7 +32,7 @@
|
||||
* radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
|
||||
* ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
|
||||
* cdc_modules.v fir_lowpass.v ddc_input_interface.v \
|
||||
* chirp_memory_loader_param.v latency_buffer.v \
|
||||
* chirp_memory_loader_param.v \
|
||||
* matched_filter_multi_segment.v matched_filter_processing_chain.v \
|
||||
* range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
|
||||
* usb_data_interface.v edge_detector.v radar_mode_controller.v
|
||||
|
||||
@@ -105,8 +105,11 @@ class RadarSettings:
|
||||
tab and Opcode enum in radar_protocol.py. This dataclass holds only
|
||||
host-side display/map settings and physical-unit conversion factors.
|
||||
|
||||
range_resolution and velocity_resolution should be calibrated to
|
||||
the actual waveform parameters.
|
||||
range_resolution and velocity_resolution below are placeholders. Live
|
||||
operation derives the actual values from WaveformConfig in
|
||||
workers.py:RadarDataWorker (see GUI-C3 fix); these literals are only
|
||||
consulted by code paths that have not yet been migrated, and should
|
||||
not be relied on for physics-accurate display.
|
||||
"""
|
||||
system_frequency: float = 10.5e9 # Hz (carrier, used for velocity calc)
|
||||
range_resolution: float = 6.0 # Meters per range bin (c/(2*Fs)*decim = 1.5*4)
|
||||
|
||||
Reference in New Issue
Block a user