Jason e67368d621 ft2232h: add frame drop counter (AUDIT-C12) + cfar RMW cadence guard (AUDIT-S22) ...

AUDIT-C12: usb_data_interface_ft2232h had a misleading single-buffer comment
that overstated the timing slack and referenced a frame_ack_toggle CDC that
was never implemented. Re-verified actual numbers: at 178 fps the slack is
1.14 ms (20%), not "much shorter than gap". No data corruption today (write
order matches read order, addresses don't collide), but frame_complete
firing while WR_FSM is still draining the previous frame causes silent
frame drops via the missed frame_ready_toggle edge.

Fix is instrumentation, not architectural rework: add wr_done_toggle
(ft_clk -> clk CDC) on WR_DONE -> WR_IDLE, track frame_pending in clk
domain, count drops in 7-bit saturating frame_drop_count, surface in
unused upper 7 bits of status_words[5]. Host now has visibility into the
failure mode if margin ever shrinks (faster frame rate or USB bandwidth
shortfall). Replaced misleading comment with corrected timing breakdown.

AUDIT-S22: cfar_ca emits one detection per 3 cycles (THR/MUL/CMP); the
detection RMW takes 3 cycles. Match by construction today, fragile against
any CFAR speedup. Added a header comment in cfar_ca.v documenting the
dependency, and a SIMULATION-only assertion in usb_data_interface_ft2232h.v
that fires [ASSERT FAIL] AUDIT-S22 if cfar_valid arrives while RMW busy.
Catches silent-drop regressions in the test suite.

Verification: new tb_ft2232h_frame_drop.v with 5 scenarios (no drops /
stalled drops / multi-drop / recovery / saturation at 127) - 10/10 PASS.
Quick regression 31/31 PASS (was 30/30; +1 new test, 0 regressions).

2026-04-29 17:51:30 +05:45

..

constraints

xdc(200t): pin AD9484 OR LVDS pair to U20/V20 (L11_T1_SRCC_14)

2026-04-29 16:01:04 +05:45

formal

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ip/xfft_2048_ip

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

scripts

chore: delete dead latency_buffer; doc cleanup for two stale comments

2026-04-28 12:52:13 +05:45

tb

ft2232h: add frame drop counter (AUDIT-C12) + cfar RMW cadence guard (AUDIT-S22)

2026-04-29 17:51:30 +05:45

.gitignore

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

ad9484_interface_400m.v

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adc_clk_mmcm_integration.md

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adc_clk_mmcm.v

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cdc_modules.v

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cfar_ca.v

ft2232h: add frame drop counter (AUDIT-C12) + cfar RMW cadence guard (AUDIT-S22)

2026-04-29 17:51:30 +05:45

chirp_memory_loader_param.v

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cic_decimator_4x_enhanced.v

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

dac_interface_single.v

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ddc_400m.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

ddc_input_interface.v

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doppler_processor.v

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edge_detector.v

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fft_engine_axi_bridge.v

fft_engine_axi_bridge: respect axi_din_tready with 1-deep skid buffer

2026-04-29 17:24:21 +05:45

fft_engine.v

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fft_twiddle_16.mem

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fft_twiddle_1024.mem

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fft_twiddle_2048.mem

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fir_lowpass.v

perf(fpga): symmetric pre-adder FIR — 32→16 DSPs/channel (-32 total)

2026-04-23 10:08:19 +05:45

fpga_self_test.v

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frequency_matched_filter.v

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long_chirp_lut.mem

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long_chirp_seg0_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg0_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

matched_filter_multi_segment.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

matched_filter_processing_chain.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

mti_canceller.v

fix(fpga): RX-F — MTI exits mute on chirp boundary, not just last bin

2026-04-23 19:58:08 +05:45

nco_400m_enhanced.v

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plfm_chirp_controller.v

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

radar_mode_controller.v

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radar_params.vh

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radar_receiver_final.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

radar_system_top_50t.v

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radar_system_top_te0712_dev.v

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radar_system_top_te0713_dev.v

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radar_system_top_te0713_umft601x_dev.v

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radar_system_top.v

fix(usb): C-9 — GUI bulk-frame parser for FT2232H + clamp inert flag bits

2026-04-29 15:12:04 +05:45

radar_transmitter.v

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range_bin_decimator.v

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run_regression.sh

ft2232h: add frame drop counter (AUDIT-C12) + cfar RMW cadence guard (AUDIT-S22)

2026-04-29 17:51:30 +05:45

rx_gain_control.v

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short_chirp_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

short_chirp_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

usb_data_interface_ft2232h.v

ft2232h: add frame drop counter (AUDIT-C12) + cfar RMW cadence guard (AUDIT-S22)

2026-04-29 17:51:30 +05:45

usb_data_interface.v

fix(fpga): TX-N9 — sim-only payload-hold checker on cmd CDC

2026-04-28 10:03:08 +05:45

xfft_16.v

…

xfft_2048.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45