Jason 5ff5671fe2 fix(fpga): TX-I — align matched-filter reference with actual post-DDC band ...

The DAC short/long chirp LUTs are 10..30 MHz upchirps (Hilbert-confirmed).
With TX_LO=10.500 GHz, RX_LO=10.380 GHz (adf4382a_manager.h) and the
120 MHz DDC NCO (ddc_400m.v), high-side mixing places the post-DDC echo
at 10..30 MHz baseband. The matched-filter reference (gen_chirp_mem.py)
was generating 0..20 MHz, implicitly assuming the chirp's low edge mixed
to DC. This caused a 10 MHz spectral offset and ~5 dB matched-filter loss.

Adds F_BASEBAND_LOW=10e6 in both gen_chirp_mem.py and radar_scene.py,
with phase formula 2*pi*F_BASEBAND_LOW*t + pi*rate*t^2 in all chirp
generators. Regenerates the 6 .mem files. Adds analyze_short_chirp_mismatch.py
for the Hilbert-based diagnosis. Fixes the misleading "30MHz to 10MHz"
comment in plfm_chirp_controller.v and adds an end-to-end frequency plan
in the LUT header.

Sideband orientation (high-side at both mixers) is the conventional choice
and consistent with antenna match (10.25..10.75 GHz, 8x16 patch designed
at 10.5 GHz). Loopback capture would settle definitively; if either mixer
is low-side the F_BASEBAND_LOW sign flips and/or chirp direction reverses.

2026-04-29 11:41:19 +05:45

..

constraints

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

formal

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ip/xfft_2048_ip

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

scripts

chore: delete dead latency_buffer; doc cleanup for two stale comments

2026-04-28 12:52:13 +05:45

tb

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

.gitignore

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

ad9484_interface_400m.v

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adc_clk_mmcm_integration.md

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adc_clk_mmcm.v

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cdc_modules.v

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cfar_ca.v

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chirp_memory_loader_param.v

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cic_decimator_4x_enhanced.v

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

dac_interface_single.v

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ddc_400m.v

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ddc_input_interface.v

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doppler_processor.v

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edge_detector.v

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fft_engine_axi_bridge.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

fft_engine.v

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fft_twiddle_16.mem

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fft_twiddle_1024.mem

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fft_twiddle_2048.mem

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fir_lowpass.v

perf(fpga): symmetric pre-adder FIR — 32→16 DSPs/channel (-32 total)

2026-04-23 10:08:19 +05:45

fpga_self_test.v

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frequency_matched_filter.v

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long_chirp_lut.mem

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long_chirp_seg0_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg0_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

matched_filter_multi_segment.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

matched_filter_processing_chain.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

mti_canceller.v

fix(fpga): RX-F — MTI exits mute on chirp boundary, not just last bin

2026-04-23 19:58:08 +05:45

nco_400m_enhanced.v

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plfm_chirp_controller.v

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

radar_mode_controller.v

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radar_params.vh

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radar_receiver_final.v

ci(fpga): wire RX-B latency tests; fix downstream compile after inline-FFT removal

2026-04-23 06:34:05 +05:45

radar_system_top_50t.v

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radar_system_top_te0712_dev.v

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radar_system_top_te0713_dev.v

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radar_system_top_te0713_umft601x_dev.v

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radar_system_top.v

fix(fpga): TX-G — surface chirps_mismatch_error to host status

2026-04-24 11:06:26 +05:45

radar_transmitter.v

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range_bin_decimator.v

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run_regression.sh

chore: delete dead latency_buffer; doc cleanup for two stale comments

2026-04-28 12:52:13 +05:45

rx_gain_control.v

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short_chirp_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

short_chirp_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

usb_data_interface_ft2232h.v

fix(fpga): TX-N9 — sim-only payload-hold checker on cmd CDC

2026-04-28 10:03:08 +05:45

usb_data_interface.v

fix(fpga): TX-N9 — sim-only payload-hold checker on cmd CDC

2026-04-28 10:03:08 +05:45

xfft_16.v

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xfft_2048.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45