Jason 853d2a5fd9 AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic ...

Pre-fix Tests 1/2/4 in fpga_self_test.v gave false PASS even on broken
silicon:

  S-19 Test 1 (CIC): `result_flags[1] <= 1'b1` unconditional, comment
       admitted "always true for simple check".
  S-20 Test 2 (FFT): `(16'sd100+16'sd100 == 16'sd200) && (...)` —
       both predicates compile-time-fold to 1; synth reduces to a
       constant write.
  S-21 Test 4 (ADC): PASS once N samples land, regardless of value.
       A stuck-at-0 / stuck-at-MAX / dead LVDS link still PASSed
       provided adc_valid_in toggled.

Fixes:

  Test 1: drive impulse {5,0,0,0,0,0,0} through registered integrator
          y[n]=y[n-1]+x[n]; require accumulator==5 after step
          response. Real adder + register path; sign-extension
          exercised. Detail = 0xC1 on fail.

  Test 2: real radix-2 butterfly with twiddle multiply across 4 FSM
          states. A=8, B=4 (real), W=2+3j -> WB=(8,12), A'=(16,12),
          B'=(0,-12). Forces synth to instantiate signed multiplier
          (DSP slice) + 17-bit signed add/sub. Detail = 0xF2 on fail.

  Test 4: track min/max across 256-sample capture, require
          (max - min) > ADC_RANGE_THRESHOLD (10 LSB). Catches stuck-at
          faults. Does NOT distinguish AD9484 format mismatches
          (audit's per-mode mean check requires SPI, impossible per
          AUDIT-C13). Detail = 0xAD on fail.

Tests:
- tb_fpga_self_test.v existing Group 1-4 (16 PASS) still pass: varied
  ADC counter input gives range >> 10.
- New Group 5: drive constant 0 -> expect Test 4 FAIL + detail=0xAD.
- New Group 6: drive constant 0x7FFF -> expect Test 4 FAIL + detail=0xAD.
- Regression: 41/41 PASS; fpga_self_test 22/22 (was 16/16).

2026-04-29 23:27:15 +05:45

..

constraints

xdc(200t): pin AD9484 OR LVDS pair to U20/V20 (L11_T1_SRCC_14)

2026-04-29 16:01:04 +05:45

formal

…

ip/xfft_2048_ip

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

scripts

chore: delete dead latency_buffer; doc cleanup for two stale comments

2026-04-28 12:52:13 +05:45

tb

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

.gitignore

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

ad9484_interface_400m.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

adc_clk_mmcm_integration.md

…

adc_clk_mmcm.v

…

cdc_modules.v

…

cfar_ca.v

cfar_ca: reset detect_count per frame (AUDIT-C6)

2026-04-29 18:09:28 +05:45

chirp_memory_loader_param.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

cic_decimator_4x_enhanced.v

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

dac_interface_single.v

…

ddc_400m.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

ddc_input_interface.v

…

doppler_processor.v

doppler: gate S_IDLE→S_ACCUMULATE on frame_start_pulse (AUDIT-S3)

2026-04-29 18:36:31 +05:45

edge_detector.v

…

fft_engine_axi_bridge.v

fft_engine_axi_bridge: respect axi_din_tready with 1-deep skid buffer

2026-04-29 17:24:21 +05:45

fft_engine.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fft_twiddle_16.mem

…

fft_twiddle_1024.mem

…

fft_twiddle_2048.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fir_lowpass.v

perf(fpga): symmetric pre-adder FIR — 32→16 DSPs/channel (-32 total)

2026-04-23 10:08:19 +05:45

fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

frequency_matched_filter.v

…

long_chirp_lut.mem

…

long_chirp_seg0_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg0_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

matched_filter_multi_segment.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

matched_filter_processing_chain.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

mti_canceller.v

fix(fpga): RX-F — MTI exits mute on chirp boundary, not just last bin

2026-04-23 19:58:08 +05:45

nco_400m_enhanced.v

…

plfm_chirp_controller.v

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

radar_mode_controller.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

radar_params.vh

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

radar_receiver_final.v

fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)

2026-04-29 19:37:37 +05:45

radar_system_top_50t.v

Revert "fix(fpga): move IBUF+BUFIO+BUFR into 50T wrapper (same scope as pad)"

2026-04-20 21:47:19 +05:45

radar_system_top_te0712_dev.v

…

radar_system_top_te0713_dev.v

…

radar_system_top_te0713_umft601x_dev.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_system_top.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_transmitter.v

…

range_bin_decimator.v

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

run_regression.sh

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

rx_gain_control.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

short_chirp_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

short_chirp_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

usb_data_interface_ft2232h.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

xfft_16.v

…

xfft_2048.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45