Jason 4f898ae63d docs(fpga): correct matched_filter_processing_chain header (LogiCORE swap, FSM) ...

The header still described the legacy in-house Radix-2 DIT fft_engine and a
FWD/REF/INV BITREV+BUTTERFLY state list that no longer matches reality.

Since RX-NEW-3 (commit 5c8cc8c), the chain instantiates fft_engine_axi_bridge,
which wraps xfft_2048 — LogiCORE FFT v9.1 (Pipelined Streaming) in synth/XSim
when FFT_USE_XILINX_IP is defined, in-house fft_engine fallback in iverilog.
Bit-reversal is now handled inside the IP (and the fallback), so the FSM has
COLLECT → SIG_FFT/CAP → REF_FFT/CAP → MULTIPLY → INV_FFT/CAP → OUTPUT → DONE.

No RTL changes. Header comment updates only.

2026-04-30 13:59:37 +05:45

..

constraints

xdc(200t): pin AD9484 OR LVDS pair to U20/V20 (L11_T1_SRCC_14)

2026-04-29 16:01:04 +05:45

formal

…

ip/xfft_2048_ip

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

scripts

chore: delete dead latency_buffer; doc cleanup for two stale comments

2026-04-28 12:52:13 +05:45

tb

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

.gitignore

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

ad9484_interface_400m.v

…

adc_clk_mmcm_integration.md

…

adc_clk_mmcm.v

…

cdc_async_fifo.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

cdc_modules.v

…

cfar_ca.v

AUDIT-C7: document GO/SO edge-bin Pfa drift in cfar_ca header

2026-04-30 08:42:32 +05:45

chirp_memory_loader_param.v

…

cic_decimator_4x_enhanced.v

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

dac_interface_single.v

…

ddc_400m.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

ddc_input_interface.v

…

doppler_processor.v

doppler: gate S_IDLE→S_ACCUMULATE on frame_start_pulse (AUDIT-S3)

2026-04-29 18:36:31 +05:45

edge_detector.v

…

fft_engine_axi_bridge.v

fft_engine_axi_bridge: respect axi_din_tready with 1-deep skid buffer

2026-04-29 17:24:21 +05:45

fft_engine.v

…

fft_twiddle_16.mem

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fft_twiddle_1024.mem

…

fft_twiddle_2048.mem

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fir_lowpass.v

AUDIT-S17: document fir_lowpass +4.96 dB DC gain and CIC-droop comp

2026-04-30 10:08:34 +05:45

fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

frequency_matched_filter.v

…

long_chirp_lut.mem

…

long_chirp_seg0_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg0_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

long_chirp_seg1_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

matched_filter_multi_segment.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

matched_filter_processing_chain.v

docs(fpga): correct matched_filter_processing_chain header (LogiCORE swap, FSM)

2026-04-30 13:59:37 +05:45

mti_canceller.v

fix(fpga): RX-F — MTI exits mute on chirp boundary, not just last bin

2026-04-23 19:58:08 +05:45

nco_400m_enhanced.v

…

plfm_chirp_controller.v

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

radar_mode_controller.v

…

radar_params.vh

…

radar_receiver_final.v

fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)

2026-04-29 19:37:37 +05:45

radar_system_top_50t.v

…

radar_system_top_te0712_dev.v

…

radar_system_top_te0713_dev.v

…

radar_system_top_te0713_umft601x_dev.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_system_top.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_transmitter.v

…

range_bin_decimator.v

AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator

2026-04-30 09:04:01 +05:45

run_regression.sh

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

rx_gain_control.v

…

short_chirp_i.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

short_chirp_q.mem

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

usb_data_interface_ft2232h.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

xfft_16.v

…

xfft_2048.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45