Jason 4f898ae63d docs(fpga): correct matched_filter_processing_chain header (LogiCORE swap, FSM) ...

The header still described the legacy in-house Radix-2 DIT fft_engine and a
FWD/REF/INV BITREV+BUTTERFLY state list that no longer matches reality.

Since RX-NEW-3 (commit 5c8cc8c), the chain instantiates fft_engine_axi_bridge,
which wraps xfft_2048 — LogiCORE FFT v9.1 (Pipelined Streaming) in synth/XSim
when FFT_USE_XILINX_IP is defined, in-house fft_engine fallback in iverilog.
Bit-reversal is now handled inside the IP (and the fallback), so the FSM has
COLLECT → SIG_FFT/CAP → REF_FFT/CAP → MULTIPLY → INV_FFT/CAP → OUTPUT → DONE.

No RTL changes. Header comment updates only.

2026-04-30 13:59:37 +05:45

..

9_1_Microcontroller

mcu(health): poll PD15 + dispatch ERROR_FPGA_DSP_STALL (AUDIT-S10 follow-up)

2026-04-29 23:42:21 +05:45

9_2_FPGA

docs(fpga): correct matched_filter_processing_chain header (LogiCORE swap, FSM)

2026-04-30 13:59:37 +05:45

9_3_GUI

fix(usb): C-9 — GUI bulk-frame parser for FT2232H + clamp inert flag bits

2026-04-29 15:12:04 +05:45

tests/cross_layer

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

tools

…