Jason 5d334bfdd6 fix(fpga): TX-N9 — sim-only payload-hold checker on cmd CDC ...

cmd_data / cmd_opcode / cmd_addr / cmd_value feed downstream CDC sync
chains; the safety property is that they only change on the cycle
cmd_valid rises (RD_PROCESS), and stay held on every other cycle so the
receiver's 2-FF synchronizer sees a clean payload regardless of where
its sample window lands. The FSM satisfies this implicitly today, but
nothing flagged a regression that introduced a stray write somewhere
in the same always block.

Added an `ifdef SIMULATION block at the bottom of both
usb_data_interface.v (FT601 / ft601_clk_in / ft601_reset_n) and
usb_data_interface_ft2232h.v (FT2232H / ft_clk / ft_reset_n). It
snapshots the payload + cmd_valid each cycle and fires
[ASSERT FAIL] TX-N9: cmd_<field> changed while cmd_valid=0 (old -> new)
on any payload change while cmd_valid is low. Local regs suffixed _n9
to avoid future name collisions. Synthesis-inert.

Quick FPGA regression unchanged: USB Data Interface 91/91 PASS, overall
28/29 (same baseline; the 1 fail is the pre-existing iverilog/Xilinx-IP
RX-NEW-3 gap).

2026-04-28 10:03:08 +05:45

..

constraints

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

formal

…

ip/xfft_2048_ip

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

scripts

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

tb

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

.gitignore

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

ad9484_interface_400m.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

adc_clk_mmcm_integration.md

…

adc_clk_mmcm.v

…

cdc_modules.v

…

cfar_ca.v

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

chirp_memory_loader_param.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

cic_decimator_4x_enhanced.v

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

dac_interface_single.v

…

ddc_400m.v

…

ddc_input_interface.v

…

doppler_processor.v

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

edge_detector.v

…

fft_engine_axi_bridge.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

fft_engine.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fft_twiddle_16.mem

…

fft_twiddle_1024.mem

…

fft_twiddle_2048.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fir_lowpass.v

perf(fpga): symmetric pre-adder FIR — 32→16 DSPs/channel (-32 total)

2026-04-23 10:08:19 +05:45

fpga_self_test.v

…

frequency_matched_filter.v

…

latency_buffer.v

…

long_chirp_lut.mem

…

long_chirp_seg0_i.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

long_chirp_seg0_q.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

long_chirp_seg1_i.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

long_chirp_seg1_q.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

matched_filter_multi_segment.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

matched_filter_processing_chain.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

mti_canceller.v

fix(fpga): RX-F — MTI exits mute on chirp boundary, not just last bin

2026-04-23 19:58:08 +05:45

nco_400m_enhanced.v

…

plfm_chirp_controller.v

fix(fpga): reset chirp_counter at DONE; source CHIRP_MAX from radar_params

2026-04-22 19:34:09 +05:45

radar_mode_controller.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

radar_params.vh

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

radar_receiver_final.v

ci(fpga): wire RX-B latency tests; fix downstream compile after inline-FFT removal

2026-04-23 06:34:05 +05:45

radar_system_top_50t.v

…

radar_system_top_te0712_dev.v

…

radar_system_top_te0713_dev.v

…

radar_system_top_te0713_umft601x_dev.v

…

radar_system_top.v

fix(fpga): TX-G — surface chirps_mismatch_error to host status

2026-04-24 11:06:26 +05:45

radar_transmitter.v

…

range_bin_decimator.v

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

run_regression.sh

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

rx_gain_control.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

short_chirp_i.mem

…

short_chirp_q.mem

…

usb_data_interface_ft2232h.v

fix(fpga): TX-N9 — sim-only payload-hold checker on cmd CDC

2026-04-28 10:03:08 +05:45

usb_data_interface.v

fix(fpga): TX-N9 — sim-only payload-hold checker on cmd CDC

2026-04-28 10:03:08 +05:45

xfft_16.v

…

xfft_2048.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45