Jason 853d2a5fd9 AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic ...

Pre-fix Tests 1/2/4 in fpga_self_test.v gave false PASS even on broken
silicon:

  S-19 Test 1 (CIC): `result_flags[1] <= 1'b1` unconditional, comment
       admitted "always true for simple check".
  S-20 Test 2 (FFT): `(16'sd100+16'sd100 == 16'sd200) && (...)` —
       both predicates compile-time-fold to 1; synth reduces to a
       constant write.
  S-21 Test 4 (ADC): PASS once N samples land, regardless of value.
       A stuck-at-0 / stuck-at-MAX / dead LVDS link still PASSed
       provided adc_valid_in toggled.

Fixes:

  Test 1: drive impulse {5,0,0,0,0,0,0} through registered integrator
          y[n]=y[n-1]+x[n]; require accumulator==5 after step
          response. Real adder + register path; sign-extension
          exercised. Detail = 0xC1 on fail.

  Test 2: real radix-2 butterfly with twiddle multiply across 4 FSM
          states. A=8, B=4 (real), W=2+3j -> WB=(8,12), A'=(16,12),
          B'=(0,-12). Forces synth to instantiate signed multiplier
          (DSP slice) + 17-bit signed add/sub. Detail = 0xF2 on fail.

  Test 4: track min/max across 256-sample capture, require
          (max - min) > ADC_RANGE_THRESHOLD (10 LSB). Catches stuck-at
          faults. Does NOT distinguish AD9484 format mismatches
          (audit's per-mode mean check requires SPI, impossible per
          AUDIT-C13). Detail = 0xAD on fail.

Tests:
- tb_fpga_self_test.v existing Group 1-4 (16 PASS) still pass: varied
  ADC counter input gives range >> 10.
- New Group 5: drive constant 0 -> expect Test 4 FAIL + detail=0xAD.
- New Group 6: drive constant 0x7FFF -> expect Test 4 FAIL + detail=0xAD.
- Regression: 41/41 PASS; fpga_self_test 22/22 (was 16/16).

2026-04-29 23:27:15 +05:45

..

cosim

cosim: refresh stale baselines (FFT-2048 + chirp realign)

2026-04-29 20:33:55 +05:45

golden

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

ad9484_interface_400m_stub.v

test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing

2026-04-20 15:48:34 +05:45

cic_dc_output.csv

…

cic_impulse_output.csv

…

cic_sine_passband.csv

…

ddc_120mhz_output.csv

…

fir_dc_output.csv

…

fir_impulse_output.csv

…

fir_sine_passband.csv

…

gen_mf_golden_ref.py

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_summary.txt

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_pipeline_output.csv

…

nco_1mhz_output.csv

…

nco_120mhz_output.csv

…

nco_freq_switch.csv

…

nco_quadrature.csv

…

radar_system_tb.v

test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing

2026-04-20 15:48:34 +05:45

tb_ad9484_xsim.v

…

tb_adc_pwdn_opcode.v

fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)

2026-04-29 19:37:37 +05:45

tb_audit_c16_num_cells.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

tb_audit_s10_gpio_split.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

tb_cdc_modules.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_cfar_ca.v

cfar_ca: reset detect_count per frame (AUDIT-C6)

2026-04-29 18:09:28 +05:45

tb_chirp_contract.v

…

tb_chirp_controller.v

test(fpga): regression coverage for C-3 and USB NUM_CELLS bugs

2026-04-22 19:44:25 +05:45

tb_cic_decimator.v

…

tb_ddc_400m.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_cosim.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_input_interface.v

…

tb_doppler_cosim.v

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

tb_doppler_frame_start_gate.v

doppler: gate S_IDLE→S_ACCUMULATE on frame_start_pulse (AUDIT-S3)

2026-04-29 18:36:31 +05:45

tb_doppler_realdata.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

tb_edge_detector.v

…

tb_fft_engine_axi_bridge.v

fft_engine_axi_bridge: respect axi_din_tready with 1-deep skid buffer

2026-04-29 17:24:21 +05:45

tb_fft_engine.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

tb_fir_lowpass.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

tb_freq_matched_filter.v

…

tb_ft2232h_frame_drop.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

tb_fullchain_realdata.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

tb_matched_filter_processing_chain.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_mf_cosim.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_mti_canceller.v

fix(fpga): RX-F — MTI exits mute on chirp boundary, not just last bin

2026-04-23 19:58:08 +05:45

tb_multiseg_cosim.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_nco_400m.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_nco_xsim.v

…

tb_radar_mode_controller.v

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

tb_radar_receiver_final.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_range_bin_decimator.v

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

tb_rx_gain_control.v

fix: 9 bugs from code review — RTL sign-ext & snapshot, thread safety, protocol fixes

2026-04-13 23:35:10 +05:45

tb_rxb_fullchain_latency.v

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

tb_rxb_latency_measure.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_system_e2e.v

chore: delete dead latency_buffer; doc cleanup for two stale comments

2026-04-28 12:52:13 +05:45

tb_threshold_detector.v

Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)

2026-03-20 04:38:35 +02:00

tb_usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

tb_xfft_2048_xsim.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45