Jason 9bed35287a AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T ...

Pre-fix usb_data_interface.v hardcoded `localparam [14:0] NUM_CELLS =
15'd16384` for the 50T 512-range x 32-doppler layout. On 200T builds
with SUPPORT_LONG_RANGE defined, RP_MAX_OUTPUT_BINS=4096 makes a real
frame 131072 cells, so the fixed value caused two distinct defects:

  (a) value: counter wrapped 8x per real frame; bit-7 frame-start
      marker fired 8x at incorrect host-frame offsets, silently
      desyncing the GUI parser
  (b) width: 15 bits could not represent 131072 (needs 17 bits)

Fix: derive NUM_CELLS = RP_MAX_OUTPUT_BINS * RP_NUM_DOPPLER_BINS and
counter width = RP_DOPPLER_MEM_ADDR_W (14 on 50T, 17 on 200T) from
radar_params.vh, so both scale together with the build define.

Tests:
- tb_audit_c16_num_cells.v: standalone counter-block exerciser (T1
  reset, T2 increment, T3 wrap at NUM_CELLS-1, T4 exactly 2 markers
  across 2*NUM_CELLS ticks, T5 top-bit observability) -- 6/6 PASS at
  both 50T (NUM_CELLS=16384, CTR_W=14) and 200T (131072, 17).
- tb_usb_data_interface.v: existing test 7-8 retargeted from the old
  hardcoded `>=15` / `==15'd16384` invariant to the new parameterized
  one (`==RP_DOPPLER_MEM_ADDR_W` / `==RP_MAX_OUTPUT_BINS*RP_NUM_DOPPLER_BINS`).

Regression: 41/41 PASS (+2 new entries: 50T default + 200T
`+define+SUPPORT_LONG_RANGE`).

2026-04-29 23:01:41 +05:45

..

cosim

cosim: refresh stale baselines (FFT-2048 + chirp realign)

2026-04-29 20:33:55 +05:45

golden

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

ad9484_interface_400m_stub.v

…

cic_dc_output.csv

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cic_impulse_output.csv

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cic_sine_passband.csv

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ddc_120mhz_output.csv

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fir_dc_output.csv

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fir_impulse_output.csv

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fir_sine_passband.csv

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gen_mf_golden_ref.py

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_summary.txt

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_pipeline_output.csv

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nco_1mhz_output.csv

…

nco_120mhz_output.csv

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nco_freq_switch.csv

…

nco_quadrature.csv

…

radar_system_tb.v

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tb_ad9484_xsim.v

…

tb_adc_pwdn_opcode.v

fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)

2026-04-29 19:37:37 +05:45

tb_audit_c16_num_cells.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

tb_audit_s10_gpio_split.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

tb_cdc_modules.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_cfar_ca.v

cfar_ca: reset detect_count per frame (AUDIT-C6)

2026-04-29 18:09:28 +05:45

tb_chirp_contract.v

…

tb_chirp_controller.v

test(fpga): regression coverage for C-3 and USB NUM_CELLS bugs

2026-04-22 19:44:25 +05:45

tb_cic_decimator.v

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tb_ddc_400m.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_cosim.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_input_interface.v

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tb_doppler_cosim.v

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tb_doppler_frame_start_gate.v

doppler: gate S_IDLE→S_ACCUMULATE on frame_start_pulse (AUDIT-S3)

2026-04-29 18:36:31 +05:45

tb_doppler_realdata.v

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tb_edge_detector.v

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tb_fft_engine_axi_bridge.v

fft_engine_axi_bridge: respect axi_din_tready with 1-deep skid buffer

2026-04-29 17:24:21 +05:45

tb_fft_engine.v

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tb_fir_lowpass.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_fpga_self_test.v

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tb_freq_matched_filter.v

…

tb_ft2232h_frame_drop.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

tb_fullchain_realdata.v

…

tb_matched_filter_processing_chain.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_mf_cosim.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_mti_canceller.v

fix(fpga): RX-F — MTI exits mute on chirp boundary, not just last bin

2026-04-23 19:58:08 +05:45

tb_multiseg_cosim.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_nco_400m.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_nco_xsim.v

…

tb_radar_mode_controller.v

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tb_radar_receiver_final.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_range_bin_decimator.v

…

tb_rx_gain_control.v

…

tb_rxb_fullchain_latency.v

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

tb_rxb_latency_measure.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_system_e2e.v

chore: delete dead latency_buffer; doc cleanup for two stale comments

2026-04-28 12:52:13 +05:45

tb_threshold_detector.v

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tb_usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

tb_xfft_2048_xsim.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45