Jason 81d6f210cb test(integration): PR-I.4 — wire new TBs into regression, retire tb_system_e2e ...

run_regression.sh replaces "System E2E (tb_system_e2e)" + "System E2E
USB_MODE=1 (FT2232H)" with the three PR-I subsuites (tb_system_opcodes,
tb_system_mechanics, tb_system_dataflow). SKIP count for --quick mode
bumped 5 -> 6 to match. "System Top USB_MODE=1 (FT2232H)" via
radar_system_tb.v is kept as a structural smoke test.

Dataflow gets --timeout=600 (vs 300 default). Its 18 ms sim takes
~430-450 s wall on this host; the 300 s default killed it at ~12.4 ms,
before the test logic block ran, yielding UNKNOWN. With 600 s, the TB
finishes cleanly and G2.2/G4.1/G4.2 all pass (3/3). The
matched_filter_multi_segment ST_WAIT_FFT hang documented in the TB
header still affects deeper coverage (G4.4 doppler, G5.x USB egress,
G9.x reset recovery), which remain deferred to PR-J.

tb_system_e2e.v removed (1294 lines) — coverage is fully replaced by
the focused subsuites; its USB_MODE=1 BFM was structurally broken
(wired only the FT601 ports, leaving the FT2232H DUT ports dangling),
which is why a USB_MODE=1 variant could "pass" without exercising the
production FT2232H path.

tb_usb_protocol_v2.v comment updated to point at tb_system_opcodes
for opcode-dispatch integration coverage.

2026-05-01 13:37:16 +05:45

..

cosim

test(cosim): T-7 strict MF thresholds + T-8 doppler 32->48 (3 sub-frames)

2026-05-01 11:49:28 +05:45

golden

…

ad9484_interface_400m_stub.v

…

cic_dc_output.csv

…

cic_impulse_output.csv

…

cic_sine_passband.csv

…

ddc_120mhz_output.csv

…

fir_dc_output.csv

…

fir_impulse_output.csv

…

fir_sine_passband.csv

…

gen_mf_golden_ref.py

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mf_golden_out_i_case1.hex

…

mf_golden_out_i_case2.hex

…

mf_golden_out_i_case3.hex

…

mf_golden_out_i_case4.hex

…

mf_golden_out_q_case1.hex

…

mf_golden_out_q_case2.hex

…

mf_golden_out_q_case3.hex

…

mf_golden_out_q_case4.hex

…

mf_golden_ref_i_case1.hex

…

mf_golden_ref_i_case2.hex

…

mf_golden_ref_i_case3.hex

…

mf_golden_ref_i_case4.hex

…

mf_golden_ref_q_case1.hex

…

mf_golden_ref_q_case2.hex

…

mf_golden_ref_q_case3.hex

…

mf_golden_ref_q_case4.hex

…

mf_golden_sig_i_case1.hex

…

mf_golden_sig_i_case2.hex

…

mf_golden_sig_i_case3.hex

…

mf_golden_sig_i_case4.hex

…

mf_golden_sig_q_case1.hex

…

mf_golden_sig_q_case2.hex

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mf_golden_sig_q_case3.hex

…

mf_golden_sig_q_case4.hex

…

mf_golden_summary.txt

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mf_pipeline_output.csv

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nco_1mhz_output.csv

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nco_120mhz_output.csv

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nco_freq_switch.csv

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nco_quadrature.csv

…

radar_system_tb.v

chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment

2026-05-01 04:35:08 +05:45

tb_ad9484_xsim.v

…

tb_adc_pwdn_opcode.v

fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)

2026-04-29 19:37:37 +05:45

tb_audit_c16_num_cells.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

tb_audit_s10_gpio_split.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

tb_cdc_async_fifo.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

tb_cdc_modules.v

…

tb_cfar_ca.v

chirp-v2 PR-F: doppler/CFAR widen to 3 sub-frames + 2-class detect

2026-05-01 03:36:03 +05:45

tb_chirp_contract.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

tb_chirp_controller.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

tb_cic_decimator.v

…

tb_ddc_400m.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_cosim.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_input_interface.v

…

tb_doppler_cosim.v

test(cosim): T-7 strict MF thresholds + T-8 doppler 32->48 (3 sub-frames)

2026-05-01 11:49:28 +05:45

tb_doppler_frame_start_gate.v

chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment

2026-05-01 04:35:08 +05:45

tb_doppler_realdata.v

test(cosim): T-7 strict MF thresholds + T-8 doppler 32->48 (3 sub-frames)

2026-05-01 11:49:28 +05:45

tb_edge_detector.v

…

tb_fft_engine_axi_bridge.v

fft_engine_axi_bridge: respect axi_din_tready with 1-deep skid buffer

2026-04-29 17:24:21 +05:45

tb_fft_engine.v

…

tb_fir_lowpass.v

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tb_fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

tb_freq_matched_filter.v

…

tb_ft2232h_frame_drop.v

chirp-v2 PR-G: header/body consistency + runtime MEDIUM ladder

2026-05-01 11:10:06 +05:45

tb_fullchain_realdata.v

chirp-v2 PR-F: doppler/CFAR widen to 3 sub-frames + 2-class detect

2026-05-01 03:36:03 +05:45

tb_matched_filter_processing_chain.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_mf_cosim.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_mti_canceller.v

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

tb_multiseg_cosim.v

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

tb_nco_400m.v

…

tb_nco_xsim.v

…

tb_radar_receiver_final.v

chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment

2026-05-01 04:35:08 +05:45

tb_range_bin_decimator.v

…

tb_rx_gain_control.v

…

tb_rxb_fullchain_latency.v

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

tb_rxb_latency_measure.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_system_dataflow.v

test(dataflow): PR-I.3 — tb_system_dataflow shallow integration probe

2026-05-01 12:50:28 +05:45

tb_system_mechanics.v

test(mechanics): PR-I.2 — tb_system_mechanics for chirp/RF/safety/CDC

2026-05-01 12:10:23 +05:45

tb_system_opcodes.v

test(opcodes): PR-I.1 — tb_system_opcodes via production FT2232H path

2026-05-01 12:07:31 +05:45

tb_threshold_detector.v

…

tb_usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

tb_usb_protocol_v2.v

test(integration): PR-I.4 — wire new TBs into regression, retire tb_system_e2e

2026-05-01 13:37:16 +05:45

tb_xfft_2048_xsim.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45