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https://github.com/NawfalMotii79/PLFM_RADAR.git
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test(dataflow): PR-I.3 — tb_system_dataflow shallow integration probe
Shallow probe verifying that auto-scan kicks the production pipeline end-of-TX-side cleanly: chirp_scheduler emits new_chirp_frame, the range pipeline (DDC + matched filter + range decimator) emits multi-bin range profiles. Recovers G2.2 (new_chirp_frame pulse), G4.1 (range_valid pulse), G4.2 (>=100 range bins) — three of T-2's sixteen hidden failures. Sim runs ~18 ms simulated (about 60-90 s wall on iverilog) — covers one full 48-chirp frame TX time. Watchdog at 25 ms. Deferred to PR-J: G4.4 doppler_valid pulse, G5.1-5.4 USB egress, G9.x reset recovery. Real finding: matched_filter_multi_segment hangs in ST_WAIT_FFT under continuous auto-scan — the inner FFT chain (xfft_2048 + frequency_matched_filter) does not assert fft_done in SIMULATION mode after the first chirp's segment completes. tb_mf_cosim still exercises the inner block in isolation (passes); the multi-segment wrapper has no dedicated TB (T-9). The hang is a production-chain integration bug, not a test infrastructure issue. This TB is NOT yet wired into run_regression.sh — that lands in PR-I.4 along with retiring tb_system_e2e.
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Jason
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`timescale 1ns / 1ps
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`include "radar_params.vh"
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// ============================================================================
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// tb_system_dataflow.v (PR-I, replaces tb_system_e2e G2.2 / G4.1 / G4.2)
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//
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// Shallow dataflow probe — verifies that auto-scan starts the production
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// pipeline cleanly: TX fires chirps, the range pipeline emits multi-bin
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// outputs through the matched filter, and observation counters advance.
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//
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// Coverage:
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// G2.2 new_chirp_frame pulsed (TX + chirp_scheduler alive)
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// G4.1 rx_range_valid pulsed (DDC + matched filter + range decimator)
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// G4.2 >= 100 range bin outputs (multi-bin emission)
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//
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// Deferred (NOT covered here — requires deeper RTL fix):
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// G4.4 doppler_valid pulse — full 48-chirp frame Doppler FFT.
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// G5.x USB header/footer egress.
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// G9.x Reset-mid-sim recovery.
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//
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// Probe runs surface a hang in matched_filter_multi_segment's
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// ST_WAIT_FFT under continuous auto-scan stimulus: the inner FFT chain
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// (xfft_2048 + frequency_matched_filter) does not assert fft_done in
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// SIMULATION mode, so segment 0/1 never advances. tb_mf_cosim still
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// exercises matched_filter_processing_chain in isolation, but the
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// multi-segment wrapper has no dedicated TB (T-9). The hang is NOT
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// a test infrastructure problem — it is a real production-chain
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// integration gap to resolve in a future PR-J pipeline pass.
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//
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// Sim budget: ~18 ms (one full 48-chirp frame TX + range pipeline drain).
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// ============================================================================
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module tb_system_dataflow;
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// ----------------------------------------------------------------------------
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// Clocks (production)
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// ----------------------------------------------------------------------------
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localparam CLK_100M_PERIOD = 10.0;
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localparam CLK_120M_PERIOD = 8.333;
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localparam FT_CLK_PERIOD = 16.667;
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localparam ADC_DCO_PERIOD = 2.5;
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reg clk_100m = 1'b0;
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reg clk_120m_dac = 1'b0;
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reg ft601_clk_in = 1'b0;
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reg adc_dco_p = 1'b0;
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reg adc_dco_n = 1'b1;
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always #(CLK_100M_PERIOD/2) clk_100m = ~clk_100m;
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always #(CLK_120M_PERIOD/2) clk_120m_dac = ~clk_120m_dac;
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always #(FT_CLK_PERIOD/2) ft601_clk_in = ~ft601_clk_in;
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always #(ADC_DCO_PERIOD/2) begin adc_dco_p = ~adc_dco_p; adc_dco_n = ~adc_dco_n; end
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// ----------------------------------------------------------------------------
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// DUT signals
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// ----------------------------------------------------------------------------
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reg reset_n = 1'b0;
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reg [7:0] adc_d_p = 8'h80;
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reg [7:0] adc_d_n = 8'h7F;
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reg stm32_new_chirp = 1'b0;
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reg stm32_new_elevation = 1'b0;
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reg stm32_new_azimuth = 1'b0;
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reg stm32_mixers_enable = 1'b0;
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reg stm32_sclk_3v3 = 1'b0;
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reg stm32_mosi_3v3 = 1'b0;
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wire stm32_miso_3v3;
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reg stm32_cs_adar1_3v3 = 1'b1, stm32_cs_adar2_3v3 = 1'b1;
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reg stm32_cs_adar3_3v3 = 1'b1, stm32_cs_adar4_3v3 = 1'b1;
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wire stm32_sclk_1v8, stm32_mosi_1v8;
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reg stm32_miso_1v8 = 1'b0;
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wire stm32_cs_adar1_1v8, stm32_cs_adar2_1v8;
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wire stm32_cs_adar3_1v8, stm32_cs_adar4_1v8;
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wire [7:0] dac_data;
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wire dac_clk;
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wire dac_sleep;
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wire fpga_rf_switch;
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wire rx_mixer_en, tx_mixer_en;
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wire adc_pwdn;
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wire adar_tx_load_1, adar_rx_load_1;
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wire adar_tx_load_2, adar_rx_load_2;
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wire adar_tx_load_3, adar_rx_load_3;
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wire adar_tx_load_4, adar_rx_load_4;
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wire adar_tr_1, adar_tr_2, adar_tr_3, adar_tr_4;
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wire [31:0] ft601_data;
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wire [3:0] ft601_be;
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wire ft601_txe_n;
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wire ft601_rxf_n;
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reg ft601_txe = 1'b0;
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reg ft601_rxf = 1'b1;
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wire ft601_wr_n;
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wire ft601_rd_n;
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wire ft601_oe_n;
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wire ft601_siwu_n;
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reg [1:0] ft601_srb = 2'b00;
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reg [1:0] ft601_swb = 2'b00;
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wire ft601_clk_out;
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wire [7:0] ft_data;
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reg ft_rxf_n = 1'b1;
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reg ft_txe_n = 1'b0;
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wire ft_rd_n;
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wire ft_wr_n;
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wire ft_oe_n;
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wire ft_siwu;
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pulldown pd[7:0] (ft_data);
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wire [5:0] current_elevation, current_azimuth, current_chirp;
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wire new_chirp_frame;
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wire [31:0] dbg_doppler_data;
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wire dbg_doppler_valid;
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wire [`RP_DOPPLER_BIN_WIDTH-1:0] dbg_doppler_bin;
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wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] dbg_range_bin;
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wire [3:0] system_status;
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wire gpio_dig5, gpio_dig6, gpio_dig7;
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// ----------------------------------------------------------------------------
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// DUT — radar_system_top with USB_MODE=1 (FT2232H production)
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// ----------------------------------------------------------------------------
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radar_system_top #(.USB_MODE(1)) dut (
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.clk_100m(clk_100m),
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.clk_120m_dac(clk_120m_dac),
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.ft601_clk_in(ft601_clk_in),
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.reset_n(reset_n),
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.dac_data(dac_data), .dac_clk(dac_clk), .dac_sleep(dac_sleep),
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.fpga_rf_switch(fpga_rf_switch),
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.rx_mixer_en(rx_mixer_en), .tx_mixer_en(tx_mixer_en),
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.adar_tx_load_1(adar_tx_load_1), .adar_rx_load_1(adar_rx_load_1),
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.adar_tx_load_2(adar_tx_load_2), .adar_rx_load_2(adar_rx_load_2),
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.adar_tx_load_3(adar_tx_load_3), .adar_rx_load_3(adar_rx_load_3),
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.adar_tx_load_4(adar_tx_load_4), .adar_rx_load_4(adar_rx_load_4),
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.adar_tr_1(adar_tr_1), .adar_tr_2(adar_tr_2),
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.adar_tr_3(adar_tr_3), .adar_tr_4(adar_tr_4),
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.stm32_sclk_3v3(stm32_sclk_3v3),
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.stm32_mosi_3v3(stm32_mosi_3v3),
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.stm32_miso_3v3(stm32_miso_3v3),
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.stm32_cs_adar1_3v3(stm32_cs_adar1_3v3),
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.stm32_cs_adar2_3v3(stm32_cs_adar2_3v3),
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.stm32_cs_adar3_3v3(stm32_cs_adar3_3v3),
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.stm32_cs_adar4_3v3(stm32_cs_adar4_3v3),
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.stm32_sclk_1v8(stm32_sclk_1v8),
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.stm32_mosi_1v8(stm32_mosi_1v8),
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.stm32_miso_1v8(stm32_miso_1v8),
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.stm32_cs_adar1_1v8(stm32_cs_adar1_1v8),
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.stm32_cs_adar2_1v8(stm32_cs_adar2_1v8),
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.stm32_cs_adar3_1v8(stm32_cs_adar3_1v8),
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.stm32_cs_adar4_1v8(stm32_cs_adar4_1v8),
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.adc_d_p(adc_d_p), .adc_d_n(adc_d_n),
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.adc_dco_p(adc_dco_p), .adc_dco_n(adc_dco_n),
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.adc_or_p(1'b0), .adc_or_n(1'b1),
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.adc_pwdn(adc_pwdn),
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.stm32_new_chirp(stm32_new_chirp),
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.stm32_new_elevation(stm32_new_elevation),
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.stm32_new_azimuth(stm32_new_azimuth),
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.stm32_mixers_enable(stm32_mixers_enable),
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.ft601_data(ft601_data),
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.ft601_be(ft601_be),
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.ft601_txe_n(ft601_txe_n),
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.ft601_rxf_n(ft601_rxf_n),
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.ft601_txe(ft601_txe),
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.ft601_rxf(ft601_rxf),
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.ft601_wr_n(ft601_wr_n),
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.ft601_rd_n(ft601_rd_n),
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.ft601_oe_n(ft601_oe_n),
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.ft601_siwu_n(ft601_siwu_n),
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.ft601_srb(ft601_srb),
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.ft601_swb(ft601_swb),
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.ft601_clk_out(ft601_clk_out),
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.ft_data(ft_data),
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.ft_rxf_n(ft_rxf_n),
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.ft_txe_n(ft_txe_n),
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.ft_rd_n(ft_rd_n),
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.ft_wr_n(ft_wr_n),
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.ft_oe_n(ft_oe_n),
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.ft_siwu(ft_siwu),
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.current_elevation(current_elevation),
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.current_azimuth(current_azimuth),
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.current_chirp(current_chirp),
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.new_chirp_frame(new_chirp_frame),
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.dbg_doppler_data(dbg_doppler_data),
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.dbg_doppler_valid(dbg_doppler_valid),
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.dbg_doppler_bin(dbg_doppler_bin),
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.dbg_range_bin(dbg_range_bin),
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.system_status(system_status),
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.gpio_dig5(gpio_dig5),
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.gpio_dig6(gpio_dig6),
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.gpio_dig7(gpio_dig7)
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);
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// ADC stimulus: ramp around mid-scale
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integer adc_phase;
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initial begin
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adc_phase = 0;
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forever begin
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@(posedge adc_dco_p);
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if (reset_n) begin
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adc_d_p = 8'h80 + ((adc_phase * 7) & 8'h3F) - 8'h20;
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adc_d_n = ~adc_d_p;
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adc_phase = adc_phase + 1;
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end else begin
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adc_d_p = 8'h80;
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adc_d_n = 8'h7F;
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end
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end
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end
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// ----------------------------------------------------------------------------
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// Observation counters
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// ----------------------------------------------------------------------------
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integer obs_chirp_frame_count = 0;
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integer obs_range_valid_count = 0;
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always @(posedge clk_100m) begin
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if (!reset_n) begin
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obs_chirp_frame_count = 0;
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obs_range_valid_count = 0;
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end else begin
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if (new_chirp_frame) obs_chirp_frame_count = obs_chirp_frame_count + 1;
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if (dut.rx_range_valid) obs_range_valid_count = obs_range_valid_count + 1;
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end
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end
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// ----------------------------------------------------------------------------
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// Test infrastructure
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// ----------------------------------------------------------------------------
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integer pass_count = 0;
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integer fail_count = 0;
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integer test_num = 0;
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task check;
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input cond;
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input [80*8-1:0] msg;
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begin
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test_num = test_num + 1;
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if (cond) begin
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$display(" [PASS] %0d: %0s", test_num, msg);
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pass_count = pass_count + 1;
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end else begin
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$display(" [FAIL] %0d: %0s", test_num, msg);
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fail_count = fail_count + 1;
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end
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end
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endtask
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// ----------------------------------------------------------------------------
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// Test sequence
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// ----------------------------------------------------------------------------
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initial begin
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$display("============================================================");
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$display(" tb_system_dataflow — TX/RX shallow integration probe");
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$display("============================================================");
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reset_n = 1'b0;
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repeat (20) @(posedge clk_100m);
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reset_n = 1'b1;
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repeat (50) @(posedge clk_100m);
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stm32_mixers_enable = 1'b1;
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$display("[%0t] mixers enabled — auto-scan running, waiting ~18 ms", $time);
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// 18 ms covers one full 48-chirp frame (3 sub-frames x 16 chirps,
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// ~8.4 ms TX) plus enough slack for new_chirp_frame to pulse and the
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// range pipeline to drain its first ~30 chirps.
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#18_000_000;
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$display("\n--- Group 2.2 / 4: TX + range pipeline ---");
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$display(" chirp_frames=%0d range_valid=%0d",
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obs_chirp_frame_count, obs_range_valid_count);
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check(obs_chirp_frame_count > 0,
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"G2.2: new_chirp_frame pulsed at least once (TX/scheduler alive)");
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check(obs_range_valid_count > 0,
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"G4.1: range_profile_valid pulsed (matched filter produced output)");
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check(obs_range_valid_count >= 100,
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"G4.2: >= 100 range profile outputs (multi-bin emission)");
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$display("\n============================================================");
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$display(" RESULTS: %0d passed, %0d failed / %0d total",
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pass_count, fail_count, test_num);
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$display(" Sim time: %0t ns", $time);
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$display("============================================================");
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if (fail_count == 0) $display(" *** ALL TESTS PASSED ***");
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else $display(" *** %0d TEST(S) FAILED ***", fail_count);
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$finish;
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end
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// Watchdog — 25 ms (~1.4x the planned 18 ms run)
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initial begin
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#25_000_000;
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$display("[WATCHDOG] tb_system_dataflow timeout at %0t", $time);
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$display(" Tests: %0d, Pass: %0d, Fail: %0d",
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test_num, pass_count, fail_count);
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$finish;
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end
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endmodule
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