Jason 7ed4d5d405 test(fpga): PR-Q.2 — align cosim T_PRI_MEDIUM 175->161 us + regen goldens ...

Mirror the PR-Q.1 PRI stagger (MEDIUM 175 us -> 161 us) into the cosim
scenario generator and regenerate all 12 affected golden hex/csv files.
Without this, the Doppler co-sim TBs would diverge from the RTL on every
MEDIUM sub-frame bin.

- tb/cosim/radar_scene.py: T_PRI_MEDIUM = 161e-6
- tb/cosim/gen_doppler_golden.py: comment update for MEDIUM bin map
- 12 regenerated hex/csv files (doppler + real_data + fullchain_realdata)

Regression: 42/0/1 (PR-Q.1 baseline preserved; T-6 SKIP is scipy-missing).

2026-05-02 14:33:23 +05:45

..

cosim

test(fpga): PR-Q.2 — align cosim T_PRI_MEDIUM 175->161 us + regen goldens

2026-05-02 14:33:23 +05:45

golden

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

ad9484_interface_400m_stub.v

fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR

2026-05-01 23:12:55 +05:45

cic_dc_output.csv

…

cic_impulse_output.csv

…

cic_sine_passband.csv

…

ddc_120mhz_output.csv

…

fir_dc_output.csv

…

fir_impulse_output.csv

…

fir_sine_passband.csv

…

gen_mf_golden_ref.py

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_summary.txt

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_pipeline_output.csv

…

nco_1mhz_output.csv

…

nco_120mhz_output.csv

…

nco_freq_switch.csv

…

nco_quadrature.csv

…

radar_system_tb.v

chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment

2026-05-01 04:35:08 +05:45

tb_ad9484_xsim.v

fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR

2026-05-01 23:12:55 +05:45

tb_adc_pwdn_opcode.v

fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)

2026-04-29 19:37:37 +05:45

tb_audit_c16_num_cells.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

tb_audit_s10_gpio_split.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

tb_cdc_async_fifo.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

tb_cdc_modules.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_cfar_ca.v

chirp-v2 PR-F: doppler/CFAR widen to 3 sub-frames + 2-class detect

2026-05-01 03:36:03 +05:45

tb_chirp_contract.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

tb_chirp_controller.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

tb_cic_decimator.v

…

tb_ddc_400m.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_cosim.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_input_interface.v

…

tb_doppler_cosim.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

tb_doppler_frame_start_gate.v

chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment

2026-05-01 04:35:08 +05:45

tb_doppler_realdata.v

test(realdata): PR-K — synthetic regen of doppler/fullchain realdata fixtures

2026-05-01 14:26:54 +05:45

tb_edge_detector.v

…

tb_fft_engine_axi_bridge.v

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45

tb_fft_engine.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

tb_fir_lowpass.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

tb_freq_matched_filter.v

…

tb_ft2232h_frame_drop.v

chirp-v2 PR-G: header/body consistency + runtime MEDIUM ladder

2026-05-01 11:10:06 +05:45

tb_fullchain_realdata.v

test(realdata): PR-K — synthetic regen of doppler/fullchain realdata fixtures

2026-05-01 14:26:54 +05:45

tb_matched_filter_processing_chain.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

tb_mf_cosim.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_mf_long_chirp.v

fix(rx): PR-J.2 — pre-collect chirp + slide segments (LONG hang)

2026-05-01 15:07:19 +05:45

tb_mti_canceller.v

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

tb_multiseg_cosim.v

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

tb_nco_400m.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_nco_xsim.v

…

tb_radar_receiver_final.v

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

tb_range_bin_decimator.v

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

tb_rx_gain_control.v

…

tb_rxb_fullchain_latency.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

tb_rxb_latency_measure.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_system_dataflow.v

test(dataflow): PR-I.3 — tb_system_dataflow shallow integration probe

2026-05-01 12:50:28 +05:45

tb_system_mechanics.v

test(mechanics): PR-I.2 — tb_system_mechanics for chirp/RF/safety/CDC

2026-05-01 12:10:23 +05:45

tb_system_opcodes.v

test(opcodes): PR-I.1 — tb_system_opcodes via production FT2232H path

2026-05-01 12:07:31 +05:45

tb_threshold_detector.v

…

tb_usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

tb_usb_protocol_v2.v

test(integration): PR-I.4 — wire new TBs into regression, retire tb_system_e2e

2026-05-01 13:37:16 +05:45

tb_xfft_2048_xsim.v

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45