Jason 53c7f416a7 cfar_ca: reset detect_count per frame (AUDIT-C6) ...

Bug: 16-bit detect_count was reset only on power-on; increments at three
sites (ST_IDLE/ST_BUFFER simple-threshold paths and ST_CFAR_CMP) accumulate
across frames. At 178 fps with even 2-3 average detections per frame the
counter wraps in 100-180 seconds, breaking any rate-based host telemetry
or health check that reads it.

Fix: add `detect_count <= 16'd0` in ST_DONE so the counter represents
"detections this frame" instead of cumulative-since-boot. Updated $display
wording from "total detections" to "frame detections".

T13 flipped from "count keeps growing" to "identical-scene frames produce
identical counts" (the actual contract a per-frame counter must satisfy).
TB snapshots detect_count during ST_DONE because cfar_busy only goes low
on ST_IDLE entry — after the reset has fired.

Verification: tb_cfar_ca 24/24 PASS, quick regression 31/31 PASS.

Note: detect_count output port is now "live" (accumulates during frame,
0 between frames). Audit confirmed no current host telemetry consumes
this port. If future host code needs a stable last-frame total, add a
detect_count_last_frame snapshot register then.

2026-04-29 18:09:28 +05:45

..

cosim

fix(fpga): TX-I — align matched-filter reference with actual post-DDC band

2026-04-29 11:41:19 +05:45

golden

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

ad9484_interface_400m_stub.v

test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing

2026-04-20 15:48:34 +05:45

cic_dc_output.csv

…

cic_impulse_output.csv

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cic_sine_passband.csv

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ddc_120mhz_output.csv

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fir_dc_output.csv

…

fir_impulse_output.csv

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fir_sine_passband.csv

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gen_mf_golden_ref.py

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_out_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_ref_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_i_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case1.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case2.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case3.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_sig_q_case4.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_golden_summary.txt

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

mf_pipeline_output.csv

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nco_1mhz_output.csv

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nco_120mhz_output.csv

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nco_freq_switch.csv

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nco_quadrature.csv

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radar_system_tb.v

test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing

2026-04-20 15:48:34 +05:45

tb_ad9484_xsim.v

…

tb_cdc_modules.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_cfar_ca.v

cfar_ca: reset detect_count per frame (AUDIT-C6)

2026-04-29 18:09:28 +05:45

tb_chirp_contract.v

…

tb_chirp_controller.v

test(fpga): regression coverage for C-3 and USB NUM_CELLS bugs

2026-04-22 19:44:25 +05:45

tb_cic_decimator.v

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tb_ddc_400m.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_cosim.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_ddc_input_interface.v

…

tb_doppler_cosim.v

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

tb_doppler_realdata.v

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tb_edge_detector.v

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tb_fft_engine_axi_bridge.v

fft_engine_axi_bridge: respect axi_din_tready with 1-deep skid buffer

2026-04-29 17:24:21 +05:45

tb_fft_engine.v

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tb_fir_lowpass.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_fpga_self_test.v

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tb_freq_matched_filter.v

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tb_ft2232h_frame_drop.v

ft2232h: add frame drop counter (AUDIT-C12) + cfar RMW cadence guard (AUDIT-S22)

2026-04-29 17:51:30 +05:45

tb_fullchain_realdata.v

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tb_matched_filter_processing_chain.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_mf_cosim.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_mti_canceller.v

fix(fpga): RX-F — MTI exits mute on chirp boundary, not just last bin

2026-04-23 19:58:08 +05:45

tb_multiseg_cosim.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_nco_400m.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

tb_nco_xsim.v

…

tb_radar_mode_controller.v

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

tb_radar_receiver_final.v

fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

2026-04-29 14:18:25 +05:45

tb_range_bin_decimator.v

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

tb_rx_gain_control.v

…

tb_rxb_fullchain_latency.v

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

tb_rxb_latency_measure.v

cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain

2026-04-27 14:06:55 +05:45

tb_system_e2e.v

chore: delete dead latency_buffer; doc cleanup for two stale comments

2026-04-28 12:52:13 +05:45

tb_threshold_detector.v

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tb_usb_data_interface.v

fix(fpga): TX-G — surface chirps_mismatch_error to host status

2026-04-24 11:06:26 +05:45

tb_xfft_2048_xsim.v

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45