mirror of
https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-08 22:47:16 +00:00
Jason
38d6dd0719
Final cleanup pass for the PR-AB.b expanded bundle. chirp_scheduler.v / radar_receiver_final.v: delete the unused subframe_pulse output + its sibling subframe_id port. Both were declared on the scheduler and bound at the radar_receiver_final.sched instance, but no downstream module read them -- doppler_processor counts sub-frame boundaries internally from new_chirp_frame + CHIRPS_PER_SUBFRAME=16. The stale "// doppler picks up in PR-F" comment was aspirational; PR-F never wired it. subframe_id demoted from output port to internal reg (still consumed by the FSM's next_enabled_subframe helper). tb_chirp_scheduler_handshake.v: drop the matching observer wires + port bindings. main.cpp: replace the F-2.1 "host_radar_mode = 2'b01 (auto-scan, FPGA-owned chirp dispatch)" boot DIAG + 8-line comment block with a short comment noting the mode register was retired in commit 1. The DIAG was asserting a register that no longer exists. Regression: - FPGA iverilog: 43/0/0 (tb_chirp_scheduler_handshake 16/16) - MCU: 51/0 (GPS) + 34/0 (AGC/safety/gap-3) Closes the PR-AB.b expanded bundle (commits 1-6) on feat/dual-range-v2.
317 lines
13 KiB
Verilog
317 lines
13 KiB
Verilog
`timescale 1ns / 1ps
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`include "radar_params.vh"
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/**
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* chirp_scheduler.v
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*
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* Single source of truth for waveform identity and inter-chirp timing on the
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* RX side. Drives `wave_sel[1:0]` and `chirp_pulse` natively; downstream
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* modules (chirp_reference_rom, matched_filter_multi_segment, mti_canceller)
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* consume those without 1-bit shims.
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*
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* Operation: FPGA-paced auto-scan over the enabled sub-frames (SHORT, MEDIUM,
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* LONG). `host_subframe_enable[2:0]` masks individual waveforms out without
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* recompiling. Each sub-frame fires `host_chirps_per_subframe` chirps at the
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* per-waveform chirp/listen-cycle setpoints.
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*
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* The legacy multi-mode field (STM32 pass-through / single-chirp debug /
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* track dwell) was retired in PR-AB.b expanded (2026-05-11). All three
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* dead branches plus their host_* inputs (host_mode, host_trigger,
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* host_debug_wave_sel, host_track_*) and the track watchdog were stripped
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* — see project_aeris10_mode_strip_2026-05-11.md for rationale.
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*
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* Pulse outputs (chirp_pulse, frame_pulse) are 1-cycle positive pulses, not
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* toggles. (A `subframe_pulse` output existed previously but was unconsumed
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* downstream — doppler_processor counts sub-frame boundaries from its own
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* 16-chirp accumulator. Removed in PR-AB.b expanded follow-up 2026-05-11.)
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*
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* PR-AB.b expanded commit 5 — beam-ready handshake: when
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* host_handshake_enable=1, the FSM enters S_BEAM_WAIT after frame_pulse
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* and only fires the next frame's first chirp once it observes an edge on
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* beam_ready_async (MCU PD8 toggle) or the ~80 ms watchdog expires.
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* Watchdog timeout sets the sticky output beam_handshake_watchdog_fired
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* (cleared only by reset_n) so the host can spot patterns falling behind
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* the chirp ladder. host_handshake_enable=0 preserves the legacy
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* always-on chirp cadence.
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*
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* Clock domain: clk (100 MHz), async-low reset.
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*/
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module chirp_scheduler (
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input wire clk,
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input wire reset_n,
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// 3-bit sub-frame enable mask (LONG|MEDIUM|SHORT)
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input wire [2:0] host_subframe_enable,
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// 3-ladder timing (100 MHz cycles). host_*_listen sums with host_guard
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// to define the inter-chirp PRI. Each waveform has independent chirp/
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// listen so SHORT can run faster while LONG covers full eclipse.
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input wire [15:0] host_short_chirp_cycles,
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input wire [15:0] host_short_listen_cycles,
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input wire [15:0] host_medium_chirp_cycles,
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input wire [15:0] host_medium_listen_cycles,
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input wire [15:0] host_long_chirp_cycles,
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input wire [15:0] host_long_listen_cycles,
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input wire [15:0] host_guard_cycles,
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// Frame structure (chirps per Doppler sub-frame, default 16)
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input wire [5:0] host_chirps_per_subframe,
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// Master enable (PR-E). When low, the scheduler holds in S_IDLE and
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// emits no chirp_pulse — the FSM resumes on the next clock edge after
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// mixers_enable returns high. Keeps the radar quiet between operator
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// commands and prevents stale chirp_pulses from being buffered by the
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// TX-side cdc_async_fifo before mixers come up.
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input wire mixers_enable,
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// PR-AB.b expanded commit 5: beam-ready handshake. beam_ready_async is the
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// raw MCU PD8 GPIO toggle (CDC-synchronized inside this module on `clk`).
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// host_handshake_enable gates whether the FSM stalls in S_BEAM_WAIT after
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// each frame_pulse. Cold-reset default at the top level is 1'b0 (legacy
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// open-loop cadence) — host enables via opcode 0x1A once the MCU's PD8
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// toggle wiring is in place.
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input wire beam_ready_async,
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input wire host_handshake_enable,
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// ====== Outputs ======
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output reg [1:0] wave_sel, // canonical waveform identity
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output reg chirp_pulse, // 1-cycle pulse: chirp begins this clk
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output reg frame_pulse, // 1-cycle pulse: frame complete
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output reg [5:0] chirp_counter, // chirp index inside current frame
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// Currently selected timing for the in-flight chirp (PR-E TX async FIFO)
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output wire [15:0] cfg_chirp_cycles,
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output wire [15:0] cfg_listen_cycles,
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output wire [15:0] cfg_guard_cycles,
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// PR-AB.b expanded commit 5: sticky handshake watchdog flag, cleared
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// only by reset_n. Plumbed into status_words[4][1] at the top level.
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output reg beam_handshake_watchdog_fired
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);
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// ============================================================================
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// Sub-frame helpers — pure functions of (subframe, mask)
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// ============================================================================
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function [1:0] first_enabled_subframe;
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input [2:0] mask;
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begin
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if (mask[0]) first_enabled_subframe = 2'd0; // SHORT
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else if (mask[1]) first_enabled_subframe = 2'd1; // MEDIUM
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else if (mask[2]) first_enabled_subframe = 2'd2; // LONG
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else first_enabled_subframe = 2'd0; // mask=000 fallback
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end
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endfunction
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function [1:0] next_enabled_subframe;
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input [1:0] cur;
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input [2:0] mask;
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reg [1:0] try0, try1, try2;
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begin
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// Walk forward from cur+1, wrapping at 3, find first enabled bit.
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try0 = (cur == 2'd2) ? 2'd0 : (cur + 2'd1);
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try1 = (try0 == 2'd2) ? 2'd0 : (try0 + 2'd1);
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try2 = (try1 == 2'd2) ? 2'd0 : (try1 + 2'd1);
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if (mask[try0]) next_enabled_subframe = try0;
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else if (mask[try1]) next_enabled_subframe = try1;
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else if (mask[try2]) next_enabled_subframe = try2;
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else next_enabled_subframe = cur; // mask=000 fallback
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end
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endfunction
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function [1:0] subframe_to_wave;
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input [1:0] sf;
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begin
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case (sf)
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2'd0: subframe_to_wave = `RP_WAVE_SHORT;
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2'd1: subframe_to_wave = `RP_WAVE_MEDIUM;
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2'd2: subframe_to_wave = `RP_WAVE_LONG;
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default: subframe_to_wave = `RP_WAVE_SHORT;
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endcase
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end
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endfunction
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// ============================================================================
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// Output mux for selected timing — wave_sel drives chirp/listen window length.
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// guard is shared across waveforms.
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// ============================================================================
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reg [15:0] sel_chirp_cycles;
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reg [15:0] sel_listen_cycles;
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always @(*) begin
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case (wave_sel)
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`RP_WAVE_SHORT: begin
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sel_chirp_cycles = host_short_chirp_cycles;
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sel_listen_cycles = host_short_listen_cycles;
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end
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`RP_WAVE_MEDIUM: begin
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sel_chirp_cycles = host_medium_chirp_cycles;
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sel_listen_cycles = host_medium_listen_cycles;
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end
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`RP_WAVE_LONG: begin
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sel_chirp_cycles = host_long_chirp_cycles;
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sel_listen_cycles = host_long_listen_cycles;
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end
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default: begin
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sel_chirp_cycles = host_short_chirp_cycles;
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sel_listen_cycles = host_short_listen_cycles;
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end
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endcase
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end
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assign cfg_chirp_cycles = sel_chirp_cycles;
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assign cfg_listen_cycles = sel_listen_cycles;
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assign cfg_guard_cycles = host_guard_cycles;
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// ============================================================================
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// Beam-ready CDC + edge detection (PR-AB.b expanded commit 5).
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// beam_ready_async is a slow MCU GPIO toggle (PD8). Two ASYNC_REG flops bring
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// it into clk, then a one-cycle delay lets us detect any transition (rising or
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// falling) — the MCU drives via HAL_GPIO_TogglePin once per beam pattern, so
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// successive frames see alternating polarities.
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// ============================================================================
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(* ASYNC_REG = "TRUE" *) reg [1:0] beam_ready_sync;
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reg beam_ready_q_prev;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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beam_ready_sync <= 2'b00;
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beam_ready_q_prev <= 1'b0;
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end else begin
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beam_ready_sync <= {beam_ready_sync[0], beam_ready_async};
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beam_ready_q_prev <= beam_ready_sync[1];
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end
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end
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wire beam_ready_q = beam_ready_sync[1];
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wire beam_ready_edge = (beam_ready_q != beam_ready_q_prev);
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// ============================================================================
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// Main FSM — auto-scan over enabled sub-frames.
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// ============================================================================
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localparam S_IDLE = 3'd0;
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localparam S_CHIRP = 3'd1;
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localparam S_LISTEN = 3'd2;
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localparam S_GUARD = 3'd3;
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localparam S_ADVANCE = 3'd4;
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localparam S_BEAM_WAIT = 3'd5;
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// Beam-ready watchdog: 23 bits at 100 MHz → ~83.9 ms = ~8 nominal frames
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// (frame ≈ 8.05 ms full 3-PRI ladder, less when subframes are masked). Long
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// enough to absorb MCU SPI bursts + scheduling jitter without auto-advancing,
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// short enough to keep the radar moving when a pattern write actually drops.
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localparam [22:0] BEAM_WATCHDOG_MAX = 23'd8_000_000;
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reg [2:0] state;
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reg [16:0] timer; // 17 bits cover LONG+listen+guard worst case
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reg [22:0] beam_watchdog; // counts clk cycles while in S_BEAM_WAIT
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reg [1:0] subframe_id; // 0=SHORT, 1=MEDIUM, 2=LONG (FSM-internal; no
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// downstream consumer needs it externally)
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// Pre-computed wires used inside the FSM advance logic so non-blocking
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// updates to subframe_id / wave_sel see the correct next value in the same
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// clock edge as the bookkeeping update.
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wire [1:0] first_sf = first_enabled_subframe(host_subframe_enable);
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wire [1:0] next_sf = next_enabled_subframe(subframe_id, host_subframe_enable);
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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state <= S_IDLE;
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timer <= 17'd0;
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wave_sel <= `RP_WAVE_SHORT;
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chirp_pulse <= 1'b0;
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frame_pulse <= 1'b0;
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chirp_counter <= 6'd0;
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subframe_id <= 2'd0;
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beam_watchdog <= 23'd0;
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beam_handshake_watchdog_fired <= 1'b0;
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end else if (!mixers_enable) begin
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// Master disable — quiesce the FSM so chirp_pulse never asserts and
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// the TX side stays at idle. beam_handshake_watchdog_fired is sticky
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// across mixers_enable cycles so the host can see late patterns even
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// after a soft restart.
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state <= S_IDLE;
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timer <= 17'd0;
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chirp_pulse <= 1'b0;
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frame_pulse <= 1'b0;
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beam_watchdog <= 23'd0;
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end else begin
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// Pulses default low — set high for one cycle on relevant transitions.
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chirp_pulse <= 1'b0;
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frame_pulse <= 1'b0;
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case (state)
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S_IDLE: begin
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timer <= 17'd0;
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chirp_counter <= 6'd0;
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subframe_id <= first_sf;
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wave_sel <= subframe_to_wave(first_sf);
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chirp_pulse <= 1'b1;
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state <= S_CHIRP;
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end
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S_CHIRP: begin
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if (timer + 17'd1 >= {1'b0, sel_chirp_cycles}) begin
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timer <= 17'd0;
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state <= S_LISTEN;
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end else timer <= timer + 17'd1;
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end
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S_LISTEN: begin
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if (timer + 17'd1 >= {1'b0, sel_listen_cycles}) begin
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timer <= 17'd0;
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state <= S_GUARD;
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end else timer <= timer + 17'd1;
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end
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S_GUARD: begin
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if (timer + 17'd1 >= {1'b0, host_guard_cycles}) begin
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timer <= 17'd0;
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state <= S_ADVANCE;
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end else timer <= timer + 17'd1;
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end
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S_ADVANCE: begin
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if (chirp_counter < host_chirps_per_subframe - 6'd1) begin
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chirp_counter <= chirp_counter + 6'd1;
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chirp_pulse <= 1'b1;
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state <= S_CHIRP;
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end else begin
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chirp_counter <= 6'd0;
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subframe_id <= next_sf;
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wave_sel <= subframe_to_wave(next_sf);
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if (next_sf == first_sf) begin
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// Frame wrap — emit frame_pulse and (if enabled) stall
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// in S_BEAM_WAIT until the MCU acknowledges via PD8.
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frame_pulse <= 1'b1;
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if (host_handshake_enable) begin
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beam_watchdog <= 23'd0;
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state <= S_BEAM_WAIT;
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end else begin
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chirp_pulse <= 1'b1;
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state <= S_CHIRP;
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end
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end else begin
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chirp_pulse <= 1'b1;
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state <= S_CHIRP;
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end
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end
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end
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S_BEAM_WAIT: begin
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// Wait for an MCU PD8 toggle (any edge) OR the watchdog.
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// host_handshake_enable can drop mid-wait — release the FSM in
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// that case so disabling the handshake never strands the
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// radar between frames.
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if (beam_ready_edge || !host_handshake_enable) begin
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beam_watchdog <= 23'd0;
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chirp_pulse <= 1'b1;
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state <= S_CHIRP;
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end else if (beam_watchdog >= BEAM_WATCHDOG_MAX) begin
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beam_handshake_watchdog_fired <= 1'b1;
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beam_watchdog <= 23'd0;
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chirp_pulse <= 1'b1;
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state <= S_CHIRP;
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end else begin
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beam_watchdog <= beam_watchdog + 23'd1;
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end
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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endmodule
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