PR-AB.b expanded commit 6: subframe_pulse strip + stale MCU DIAG cleanup

Final cleanup pass for the PR-AB.b expanded bundle.

chirp_scheduler.v / radar_receiver_final.v: delete the unused subframe_pulse
output + its sibling subframe_id port. Both were declared on the scheduler
and bound at the radar_receiver_final.sched instance, but no downstream
module read them -- doppler_processor counts sub-frame boundaries
internally from new_chirp_frame + CHIRPS_PER_SUBFRAME=16. The stale
"// doppler picks up in PR-F" comment was aspirational; PR-F never wired
it. subframe_id demoted from output port to internal reg (still consumed
by the FSM's next_enabled_subframe helper).

tb_chirp_scheduler_handshake.v: drop the matching observer wires + port
bindings.

main.cpp: replace the F-2.1 "host_radar_mode = 2'b01 (auto-scan, FPGA-owned
chirp dispatch)" boot DIAG + 8-line comment block with a short comment
noting the mode register was retired in commit 1. The DIAG was asserting a
register that no longer exists.

Regression:
- FPGA iverilog: 43/0/0 (tb_chirp_scheduler_handshake 16/16)
- MCU: 51/0 (GPS) + 34/0 (AGC/safety/gap-3)

Closes the PR-AB.b expanded bundle (commits 1-6) on feat/dual-range-v2.

9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp

@@ -1857,15 +1857,11 @@ int main(void)
   HAL_GPIO_WritePin(GPIOD, GPIO_PIN_12, GPIO_PIN_SET);
   DIAG("FPGA", "FPGA reset complete -- adar_tr_x driven LOW (RX commanded)");
 
-  /* F-2.1: this firmware build supports only FPGA mode 2'b01 (RP_MODE_AUTO_3KM,
-   * the cold-reset default at radar_system_top.v:1058). The MCU does not
-   * dispatch chirps -- chirp_scheduler.v owns the SHORT/MEDIUM/LONG ladder.
-   * Mode 2'b00 (STM32 pass-through) is supported on the FPGA side but is
-   * NOT implemented in this firmware: a real pass-through would need a
-   * hardware-timer-driven PD8 emitter (software delay_us is too jittery
-   * for Doppler) plus MCU<->FPGA agreement on host_chirps_per_subframe.
-   * Operators must not change host_radar_mode away from 2'b01. */
-  DIAG("FPGA", "Production mode: host_radar_mode = 2'b01 (auto-scan, FPGA-owned chirp dispatch)");
+  /* The MCU does not dispatch chirps -- chirp_scheduler.v owns the
+   * SHORT/MEDIUM/LONG ladder unconditionally. The legacy host_radar_mode
+   * register and its 2'b00 (STM32 pass-through) / 2'b10 (single-chirp debug)
+   * / 2'b11 (track dwell) branches were retired in PR-AB.b expanded commit 1
+   * (2026-05-11); auto-scan is now the only behavior. */
 
 // Initialize module IMU
   DIAG_SECTION("IMU INIT (GY-85)");

9_Firmware/9_2_FPGA/chirp_scheduler.v

@@ -21,8 +21,10 @@
  * host_debug_wave_sel, host_track_*) and the track watchdog were stripped
  * — see project_aeris10_mode_strip_2026-05-11.md for rationale.
  *
- * Pulse outputs (chirp_pulse, subframe_pulse, frame_pulse) are 1-cycle
- * positive pulses, not toggles.
+ * Pulse outputs (chirp_pulse, frame_pulse) are 1-cycle positive pulses, not
+ * toggles. (A `subframe_pulse` output existed previously but was unconsumed
+ * downstream — doppler_processor counts sub-frame boundaries from its own
+ * 16-chirp accumulator. Removed in PR-AB.b expanded follow-up 2026-05-11.)
  *
  * PR-AB.b expanded commit 5 — beam-ready handshake: when
  * host_handshake_enable=1, the FSM enters S_BEAM_WAIT after frame_pulse
@@ -76,10 +78,8 @@ module chirp_scheduler (
     // ====== Outputs ======
     output reg  [1:0]  wave_sel,         // canonical waveform identity
     output reg         chirp_pulse,      // 1-cycle pulse: chirp begins this clk
-    output reg         subframe_pulse,   // 1-cycle pulse: sub-frame complete
     output reg         frame_pulse,      // 1-cycle pulse: frame complete
     output reg  [5:0]  chirp_counter,    // chirp index inside current frame
-    output reg  [1:0]  subframe_id,      // 0=SHORT, 1=MEDIUM, 2=LONG
 
     // Currently selected timing for the in-flight chirp (PR-E TX async FIFO)
     output wire [15:0] cfg_chirp_cycles,
@@ -202,6 +202,8 @@ localparam [22:0] BEAM_WATCHDOG_MAX = 23'd8_000_000;
 reg [2:0]  state;
 reg [16:0] timer;             // 17 bits cover LONG+listen+guard worst case
 reg [22:0] beam_watchdog;     // counts clk cycles while in S_BEAM_WAIT
+reg [1:0]  subframe_id;       // 0=SHORT, 1=MEDIUM, 2=LONG (FSM-internal; no
+                              // downstream consumer needs it externally)
 
 // Pre-computed wires used inside the FSM advance logic so non-blocking
 // updates to subframe_id / wave_sel see the correct next value in the same
@@ -215,7 +217,6 @@ always @(posedge clk or negedge reset_n) begin
         timer          <= 17'd0;
         wave_sel       <= `RP_WAVE_SHORT;
         chirp_pulse    <= 1'b0;
-        subframe_pulse <= 1'b0;
         frame_pulse    <= 1'b0;
         chirp_counter  <= 6'd0;
         subframe_id    <= 2'd0;
@@ -229,13 +230,11 @@ always @(posedge clk or negedge reset_n) begin
         state          <= S_IDLE;
         timer          <= 17'd0;
         chirp_pulse    <= 1'b0;
-        subframe_pulse <= 1'b0;
         frame_pulse    <= 1'b0;
         beam_watchdog  <= 23'd0;
     end else begin
         // Pulses default low — set high for one cycle on relevant transitions.
         chirp_pulse    <= 1'b0;
-        subframe_pulse <= 1'b0;
         frame_pulse    <= 1'b0;
 
         case (state)
@@ -272,7 +271,6 @@ always @(posedge clk or negedge reset_n) begin
                     state         <= S_CHIRP;
                 end else begin
                     chirp_counter  <= 6'd0;
-                    subframe_pulse <= 1'b1;
                     subframe_id    <= next_sf;
                     wave_sel       <= subframe_to_wave(next_sf);
                     if (next_sf == first_sf) begin

9_Firmware/9_2_FPGA/radar_receiver_final.v

@@ -143,10 +143,8 @@ module radar_receiver_final (
 // no use_long_chirp shim and no mc_new_*-toggle XOR converters.
 wire [1:0] wave_sel;
 wire chirp_pulse;
-wire subframe_pulse;       // unused on RX in PR-D; doppler picks up in PR-F
-wire frame_pulse;          // unused on RX in PR-D; PR-F doppler driver
+wire frame_pulse;          // forwarded to TX-side CDC + top-level dwell-sync pin
 wire [5:0] sched_chirp_counter;
-wire [1:0] sched_subframe_id;
 wire [15:0] sched_cfg_chirp_cycles, sched_cfg_listen_cycles, sched_cfg_guard_cycles;
 
 wire [1:0] segment_request;
@@ -252,10 +250,8 @@ chirp_scheduler sched (
     .host_handshake_enable(host_handshake_enable),
     .wave_sel(wave_sel),
     .chirp_pulse(chirp_pulse),
-    .subframe_pulse(subframe_pulse),
     .frame_pulse(frame_pulse),
     .chirp_counter(sched_chirp_counter),
-    .subframe_id(sched_subframe_id),
     .cfg_chirp_cycles (sched_cfg_chirp_cycles),
     .cfg_listen_cycles(sched_cfg_listen_cycles),
     .cfg_guard_cycles (sched_cfg_guard_cycles),

9_Firmware/9_2_FPGA/tb/tb_chirp_scheduler_handshake.v

@@ -40,10 +40,8 @@ reg         handshake_enable = 1'b0;
 
 wire [1:0]  wave_sel;
 wire        chirp_pulse;
-wire        subframe_pulse;
 wire        frame_pulse;
 wire [5:0]  chirp_counter;
-wire [1:0]  subframe_id;
 wire [15:0] cfg_chirp_cycles;
 wire [15:0] cfg_listen_cycles;
 wire [15:0] cfg_guard_cycles;
@@ -66,10 +64,8 @@ chirp_scheduler dut (
     .host_handshake_enable        (handshake_enable),
     .wave_sel                     (wave_sel),
     .chirp_pulse                  (chirp_pulse),
-    .subframe_pulse               (subframe_pulse),
     .frame_pulse                  (frame_pulse),
     .chirp_counter                (chirp_counter),
-    .subframe_id                  (subframe_id),
     .cfg_chirp_cycles             (cfg_chirp_cycles),
     .cfg_listen_cycles            (cfg_listen_cycles),
     .cfg_guard_cycles             (cfg_guard_cycles),