Jason f9e64c420b docs(fpga): PR-X.2 F-7.1 — delete stale MMCM integration recipe ...

adc_clk_mmcm_integration.md was a 164-line "Step 1: modify
ad9484_interface_400m.v / Replace the BUFG instantiation with
adc_clk_mmcm" walkthrough for an integration that is already
shipped in the production RTL.

ad9484_interface_400m.v lines 68-102 already document the BUFIO/BUFG/
MMCME2 topology inline ("MMCME2 jitter-cleaning wrapper replaces the
direct BUFG. The PLL feedback loop attenuates input jitter from ~50 ps
to ~20-30 ps..."). adc_clk_mmcm.v has the wrapper itself with its own
header. constraints/adc_clk_mmcm.xdc carries the timing rationale.

A future engineer reading the integration recipe could mistake the
already-integrated feature for unfinished work and try to redo the
"Step 1: modify" edits — actively harmful.

2026-05-05 13:44:43 +05:45

..

9_1_Microcontroller

refactor(mcu): PR-W F-6.7 — privatize setADTR1107Mode

2026-05-05 11:30:46 +05:45

9_2_FPGA

docs(fpga): PR-X.2 F-7.1 — delete stale MMCM integration recipe

2026-05-05 13:44:43 +05:45

9_3_GUI

test(v7): port live-vs-replay physical-units parity guard from develop

2026-05-05 09:30:26 +05:45

tests/cross_layer

chore(tests): retire v1 cross-layer iverilog cosim tier

2026-05-04 21:06:34 +05:45

tools

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