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docs(fpga): PR-X.2 F-7.1 — delete stale MMCM integration recipe
adc_clk_mmcm_integration.md was a 164-line "Step 1: modify
ad9484_interface_400m.v / Replace the BUFG instantiation with
adc_clk_mmcm" walkthrough for an integration that is already
shipped in the production RTL.
ad9484_interface_400m.v lines 68-102 already document the BUFIO/BUFG/
MMCME2 topology inline ("MMCME2 jitter-cleaning wrapper replaces the
direct BUFG. The PLL feedback loop attenuates input jitter from ~50 ps
to ~20-30 ps..."). adc_clk_mmcm.v has the wrapper itself with its own
header. constraints/adc_clk_mmcm.xdc carries the timing rationale.
A future engineer reading the integration recipe could mistake the
already-integrated feature for unfinished work and try to redo the
"Step 1: modify" edits — actively harmful.
This commit is contained in:
Jason
@@ -1,164 +0,0 @@
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# ADC Clock MMCM Integration Guide
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## Overview
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`adc_clk_mmcm.v` is a drop-in MMCME2_ADV wrapper that replaces the direct BUFG
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on the 400 MHz ADC data clock output with a jitter-cleaning PLL loop.
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### Current clock path (Build 18)
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```
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adc_dco_p/n → IBUFDS → BUFIO (drives IDDR only — near-zero delay)
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→ BUFG (drives all fabric 400 MHz logic)
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```
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### New clock path (with MMCM)
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```
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adc_dco_p/n → IBUFDS → BUFIO (unchanged — drives IDDR only)
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→ MMCME2 CLKIN1 → CLKOUT0 → BUFG (fabric 400 MHz)
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→ CLKFBOUT → BUFG → CLKFBIN (feedback)
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```
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## Expected Timing Improvement
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| Parameter | Before (Build 18) | After (estimated) |
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|-----------|-------------------|-------------------|
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| Input jitter | 50 ps | 50 ps (unchanged) |
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| Output jitter (MMCM) | N/A | ~20-30 ps |
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| Clock uncertainty | 43 ps | ~25 ps |
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| WNS (setup, 400 MHz) | +0.062 ns | ~+0.08 to +0.10 ns |
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| WHS (hold, 100 MHz) | +0.059 ns | unchanged |
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The improvement comes from reduced clock uncertainty in the Vivado timing
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analysis. The MMCM's PLL loop attenuates the input jitter, so Vivado deducts
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less uncertainty from the timing budget.
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## MMCM Configuration
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```
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CLKIN1 = 400 MHz (2.500 ns)
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DIVCLK_DIVIDE = 1
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CLKFBOUT_MULT_F = 2.0 → VCO = 800 MHz
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CLKOUT0_DIVIDE_F = 2.0 → Output = 400 MHz
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BANDWIDTH = HIGH (maximum jitter filtering)
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```
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VCO at 800 MHz is well within the Artix-7 -2 speed grade range (600–1200 MHz).
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## Resource Cost
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| Resource | Count | Notes |
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|----------|-------|-------|
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| MMCME2_ADV | 1 | Was 0/10, now 1/10 |
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| BUFG | +1 (feedback) | Was 4/32, now 5/32 |
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| FFs | 0 | No additional fabric registers |
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## Integration Steps
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### Step 1: Modify `ad9484_interface_400m.v`
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Replace the BUFG instantiation with `adc_clk_mmcm`:
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```verilog
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// REMOVE these lines (65-69):
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// BUFG bufg_dco (
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// .I(adc_dco),
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// .O(adc_dco_buffered)
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// );
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// assign adc_dco_bufg = adc_dco_buffered;
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// ADD this instead:
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wire mmcm_locked;
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wire adc_dco_mmcm;
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adc_clk_mmcm mmcm_inst (
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.clk_in (adc_dco), // From IBUFDS output
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.reset_n (reset_n),
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.clk_400m_out (adc_dco_mmcm), // Jitter-cleaned 400 MHz
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.mmcm_locked (mmcm_locked)
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);
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// Use MMCM output for all fabric logic
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wire adc_dco_buffered = adc_dco_mmcm;
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assign adc_dco_bufg = adc_dco_buffered;
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```
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### Step 2: Gate reset on MMCM lock (recommended)
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In `ad9484_interface_400m.v`, modify the reset synchronizer to require MMCM lock:
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```verilog
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// Change the reset synchronizer input from:
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// always @(posedge adc_dco_buffered or negedge reset_n) begin
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// if (!reset_n)
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// reset_sync_400m <= 2'b00;
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// else
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// reset_sync_400m <= {reset_sync_400m[0], 1'b1};
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// end
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// To:
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wire reset_n_gated = reset_n & mmcm_locked;
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always @(posedge adc_dco_buffered or negedge reset_n_gated) begin
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if (!reset_n_gated)
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reset_sync_400m <= 2'b00;
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else
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reset_sync_400m <= {reset_sync_400m[0], 1'b1};
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end
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```
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This ensures the 400 MHz domain stays in reset until the MMCM has locked and
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the clock is stable. Without this, the first ~10 µs after power-up (before
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MMCM lock) could produce glitchy clock edges.
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### Step 3: Add constraint file
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Add `constraints/adc_clk_mmcm.xdc` to the Vivado project. Uncomment the
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constraints and adjust hierarchy paths based on your actual instantiation.
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Key constraints to uncomment:
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1. `create_generated_clock` (or verify Vivado auto-creates it)
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2. `set_max_delay` between `adc_dco_p` and `clk_400m_mmcm`
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3. `set_false_path` between `clk_400m_mmcm` and other clock domains
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4. `set_false_path` on `LOCKED` output
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### Step 4: Add to build script
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In the Tcl build script, add the new source file:
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```tcl
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read_verilog adc_clk_mmcm.v
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read_xdc constraints/adc_clk_mmcm.xdc
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```
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### Step 5: Verify
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After building:
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1. Check `report_clocks` — should show the new MMCM-derived clock
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2. Check `report_clock_interaction` — verify no unexpected crossings
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3. Check WNS on the `adc_dco_p` / MMCM clock group — should improve
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4. Check MMCM locked in ILA during bring-up
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## BUFIO Compatibility Note
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The BUFIO path for IDDR capture is **not affected** by this change. BUFIO
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drives only IOB primitives (IDDR) and cannot go through an MMCM. The BUFIO
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continues to use the raw IBUFDS output with near-zero insertion delay, which
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is correct for source-synchronous DDR capture.
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The re-registration from BUFIO domain to BUFG domain (lines 105-108 of
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`ad9484_interface_400m.v`) now crosses from the raw `adc_dco_p` clock to the
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MMCM-derived clock. Since both are frequency-matched and the MMCM is locked
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to the input, this is a safe single-register transfer. The `set_max_delay`
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constraint in the XDC ensures Vivado verifies this.
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## Simulation
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Under `SIMULATION` define (iverilog), the module passes the clock straight
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through with a simulated lock delay of ~4096 cycles. This matches the
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current testbench behavior — no changes to any testbenches needed.
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## Rollback
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To revert: simply restore the original BUFG in `ad9484_interface_400m.v` and
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remove `adc_clk_mmcm.v` + `constraints/adc_clk_mmcm.xdc` from the project.
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No other files are affected.
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