Jason b3b4580e9c xdc(200t): pin AD9484 OR LVDS pair to U20/V20 (L11_T1_SRCC_14) ...

Closes AUDIT-C15. The 200T XDC `adc_or_p/n` PACKAGE_PIN was a TODO
placeholder that blocked all 200T synth/impl with unplaced-IO errors.

Pins U20/V20 are L11P/L11N_T1_SRCC_14 — same T1 clock tile as adc_dco_p
on L12_MRCC (W19/W20), so OR captures with the same IBUFDS->BUFIO->IDDR
source-synchronous topology as adc_d_p[*]. Free-pair confirmed by Vivado
get_package_pins query against xc7a200tfbg484-2.

Adds DIFF_TERM TRUE on adc_or_n (was only on the p-side; explicit on
both is safer). Adds input_delay constraints mirroring adc_d_p
(max 1.0 ns / min 0.2 ns on both edges).

Header pin counts updated: Bank 14 21/50 used, total 184/285.

This is the FPGA-team RECOMMENDATION for the production PCB (NEW
design); the PCB designer must route AD9484 OR+ -> U20 and OR- -> V20.

Validation:
- read_xdc + link_design -part xc7a200tfbg484-2 -> READ OK on both
  xc7a200t_fbg484.xdc and adc_clk_mmcm.xdc; no PACKAGE_PIN errors.
- ./run_regression.sh --quick: 29/29 PASS (RTL untouched).

2026-04-29 16:01:04 +05:45

..

9_1_Microcontroller

fix(mcu): MCU-A4 — BKPSRAM warm-restart bypass for OCXO 180 s warmup

2026-04-28 09:50:32 +05:45

9_2_FPGA

xdc(200t): pin AD9484 OR LVDS pair to U20/V20 (L11_T1_SRCC_14)

2026-04-29 16:01:04 +05:45

9_3_GUI

fix(usb): C-9 — GUI bulk-frame parser for FT2232H + clamp inert flag bits

2026-04-29 15:12:04 +05:45

tests/cross_layer

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

tools

fix: enforce strict ruff lint (17 rule sets) across entire repo

2026-04-12 14:21:03 +05:45