mirror of
https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-08 14:44:56 +00:00
Jason
ae61cf5dc5
Regression coverage additions in run_regression.sh:
- Phase 2: tb_ddc_400m (standalone DDC unit, 7 checks)
- Phase 3: tb_freq_matched_filter (14 checks)
- Phase 4: tb_ddc_input_interface (26 checks), tb_latency_buffer
(13 checks)
All four existed in tb/ but had no regression runner entry; now gate
every push/PR. Deletes tb/tb_multiseg_cosim.v — stale against the
current RP_FFT_SIZE=2048 / RP_LONG_SEGMENTS_3KM=2 (TB hardcoded 1024/4,
15/32 checks fail on current RTL). Re-add when the multi-segment TB
is reworked for the 2048-point pipeline.
CI: new fpga-fuzz job running test_ddc_cosim_fuzz.py -m slow
(100-seed sweep). Gated to schedule (07:00 UTC daily) +
workflow_dispatch so PRs stay fast.
151 lines
4.5 KiB
YAML
151 lines
4.5 KiB
YAML
name: AERIS-10 CI
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on:
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pull_request:
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branches: [main, develop]
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push:
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branches: [main, develop]
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schedule:
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- cron: "0 7 * * *" # Nightly 07:00 UTC — slow-path fuzz
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workflow_dispatch:
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jobs:
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# ===========================================================================
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# Python: lint (ruff), syntax check (py_compile), unit tests (pytest)
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# CI structure proposed by hcm444 — uses uv for dependency management
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# ===========================================================================
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python-tests:
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name: Python Lint + Tests
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- uses: actions/setup-python@v5
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with:
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python-version: "3.12"
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- uses: astral-sh/setup-uv@v5
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- name: Install dependencies
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run: uv sync --group dev
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- name: Ruff lint (whole repo)
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run: uv run ruff check .
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- name: Syntax check (py_compile)
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run: |
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uv run python - <<'PY'
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import py_compile
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from pathlib import Path
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skip = {".git", "__pycache__", ".venv", "venv", "docs"}
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for p in Path(".").rglob("*.py"):
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if skip & set(p.parts):
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continue
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py_compile.compile(str(p), doraise=True)
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PY
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- name: Unit tests
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run: >
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uv run pytest
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9_Firmware/9_3_GUI/test_GUI_V65_Tk.py
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9_Firmware/9_3_GUI/test_v7.py
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-v --tb=short
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# ===========================================================================
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# MCU Firmware Unit Tests (20 tests)
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# Bug regression (15) + Gap-3 safety tests (5)
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# ===========================================================================
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mcu-tests:
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name: MCU Firmware Tests
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- name: Install build tools
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run: sudo apt-get update && sudo apt-get install -y build-essential
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- name: Build and run MCU tests
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run: make test
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working-directory: 9_Firmware/9_1_Microcontroller/tests
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# ===========================================================================
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# FPGA RTL Regression (25 testbenches + lint)
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# ===========================================================================
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fpga-regression:
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name: FPGA Regression
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- name: Install Icarus Verilog
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run: sudo apt-get update && sudo apt-get install -y iverilog
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- name: Run full FPGA regression
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run: bash run_regression.sh
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working-directory: 9_Firmware/9_2_FPGA
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# ===========================================================================
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# Cross-Layer Contract Tests (Python ↔ Verilog ↔ C)
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# Validates opcode maps, bit widths, packet layouts, and round-trip
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# correctness across FPGA RTL, Python GUI, and STM32 firmware.
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# ===========================================================================
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cross-layer-tests:
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name: Cross-Layer Contract Tests
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- uses: actions/setup-python@v5
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with:
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python-version: "3.12"
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- uses: astral-sh/setup-uv@v5
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- name: Install dependencies
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run: uv sync --group dev
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- name: Install Icarus Verilog
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run: sudo apt-get update && sudo apt-get install -y iverilog
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- name: Run cross-layer contract tests
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run: >
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uv run pytest
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9_Firmware/tests/cross_layer/test_cross_layer_contract.py
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-v --tb=short
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# ===========================================================================
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# DDC Co-Sim Fuzz (slow, nightly + manual dispatch only)
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# 100 random seeds through the full DDC pipeline vs Python radar_scene model.
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# Gated on schedule/workflow_dispatch to keep PRs fast; skipped on push/PR.
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# ===========================================================================
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fpga-fuzz:
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name: FPGA DDC Fuzz (slow)
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runs-on: ubuntu-latest
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if: github.event_name == 'schedule' || github.event_name == 'workflow_dispatch'
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steps:
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- uses: actions/checkout@v4
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- uses: actions/setup-python@v5
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with:
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python-version: "3.12"
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- uses: astral-sh/setup-uv@v5
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- name: Install dependencies
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run: uv sync --group dev
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- name: Install Icarus Verilog
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run: sudo apt-get update && sudo apt-get install -y iverilog
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- name: Run DDC fuzz (100-seed sweep)
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run: >
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uv run pytest -m slow
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9_Firmware/tests/cross_layer/test_ddc_cosim_fuzz.py
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-v --tb=short
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