name: AERIS-10 CI on: pull_request: branches: [main, develop] push: branches: [main, develop] schedule: - cron: "0 7 * * *" # Nightly 07:00 UTC — slow-path fuzz workflow_dispatch: jobs: # =========================================================================== # Python: lint (ruff), syntax check (py_compile), unit tests (pytest) # CI structure proposed by hcm444 — uses uv for dependency management # =========================================================================== python-tests: name: Python Lint + Tests runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - uses: actions/setup-python@v5 with: python-version: "3.12" - uses: astral-sh/setup-uv@v5 - name: Install dependencies run: uv sync --group dev - name: Ruff lint (whole repo) run: uv run ruff check . - name: Syntax check (py_compile) run: | uv run python - <<'PY' import py_compile from pathlib import Path skip = {".git", "__pycache__", ".venv", "venv", "docs"} for p in Path(".").rglob("*.py"): if skip & set(p.parts): continue py_compile.compile(str(p), doraise=True) PY - name: Unit tests run: > uv run pytest 9_Firmware/9_3_GUI/test_GUI_V65_Tk.py 9_Firmware/9_3_GUI/test_v7.py -v --tb=short # =========================================================================== # MCU Firmware Unit Tests (20 tests) # Bug regression (15) + Gap-3 safety tests (5) # =========================================================================== mcu-tests: name: MCU Firmware Tests runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - name: Install build tools run: sudo apt-get update && sudo apt-get install -y build-essential - name: Build and run MCU tests run: make test working-directory: 9_Firmware/9_1_Microcontroller/tests # =========================================================================== # FPGA RTL Regression (25 testbenches + lint) # =========================================================================== fpga-regression: name: FPGA Regression runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - name: Install Icarus Verilog run: sudo apt-get update && sudo apt-get install -y iverilog - name: Run full FPGA regression run: bash run_regression.sh working-directory: 9_Firmware/9_2_FPGA # =========================================================================== # Cross-Layer Contract Tests (Python ↔ Verilog ↔ C) # Validates opcode maps, bit widths, packet layouts, and round-trip # correctness across FPGA RTL, Python GUI, and STM32 firmware. # =========================================================================== cross-layer-tests: name: Cross-Layer Contract Tests runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - uses: actions/setup-python@v5 with: python-version: "3.12" - uses: astral-sh/setup-uv@v5 - name: Install dependencies run: uv sync --group dev - name: Install Icarus Verilog run: sudo apt-get update && sudo apt-get install -y iverilog - name: Run cross-layer contract tests run: > uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py -v --tb=short # =========================================================================== # DDC Co-Sim Fuzz (slow, nightly + manual dispatch only) # 100 random seeds through the full DDC pipeline vs Python radar_scene model. # Gated on schedule/workflow_dispatch to keep PRs fast; skipped on push/PR. # =========================================================================== fpga-fuzz: name: FPGA DDC Fuzz (slow) runs-on: ubuntu-latest if: github.event_name == 'schedule' || github.event_name == 'workflow_dispatch' steps: - uses: actions/checkout@v4 - uses: actions/setup-python@v5 with: python-version: "3.12" - uses: astral-sh/setup-uv@v5 - name: Install dependencies run: uv sync --group dev - name: Install Icarus Verilog run: sudo apt-get update && sudo apt-get install -y iverilog - name: Run DDC fuzz (100-seed sweep) run: > uv run pytest -m slow 9_Firmware/tests/cross_layer/test_ddc_cosim_fuzz.py -v --tb=short