Jason
9d1eb4b11c
FPGA — RX chain
matched_filter_multi_segment.v: drop the gratuitous /4 scaling on
DDC sign-extended input (was ddc_i[17:2] + ddc_i[1]); use
ddc_i[15:0] directly. fft_engine has INTERNAL_W=32 with
saturating 16-bit output, so full 16-bit input is safe. Restores
~12 dB of MF input dynamic range.
radar_receiver_final.v: remove latency_buffer (count-N-pulses-then-
prime FIFO that left frame 1 with all-zero ref). Replaced with
a single-FF alignment register on ref_i/ref_q that matches the
1-FF stage multi_segment ST_PROCESSING uses on adc_data.
Verified by tb/tb_rxb_fullchain_latency.v — autocorrelation peak
at bin 0 with peak/mean ~88x.
doppler_processor.v / mti_canceller.v / cfar_ca.v /
range_bin_decimator.v / radar_receiver_final.v / radar_system_top.v
/ usb_data_interface_ft2232h.v: switch port and parameter widths
from RP_NUM_RANGE_BINS / RP_RANGE_BIN_BITS (always 512 / 9-bit)
to RP_MAX_OUTPUT_BINS / RP_RANGE_BIN_WIDTH_MAX (auto-scales:
50T 512 / 9-bit, 200T 4096 / 12-bit). Unblocks 200T 20 km mode
at the RX module boundary; USB wire-protocol extension still
pending.
radar_receiver_final.v: doppler_frame_done_prev reset value 0 -> 1
to prevent false done pulse on cycle 1 when level signal is
HIGH at reset.
matched_filter_processing_chain.v: delete the broken `ifdef
SIMULATION inline behavioural FFT (482 lines removed). It
produced wrong-bin peaks and 100-1000x weak magnitudes. Chain
now uses production fft_engine.v + frequency_matched_filter.v
in both iverilog and Vivado. Iverilog tests are ~38x slower per
chain pass but produce correct results. Misleading "OK with
Xilinx IP" comments at three test sites updated since the FFT
is in-house, not an IP placeholder.
FPGA — testbenches
tb/tb_rxb_latency_measure.v (new): measures chain internal pipeline
depth (~2057 cycles, chirp-agnostic).
tb/tb_rxb_fullchain_latency.v (new): full-chain autocorrelation
verification — drives ddc with the same chirp samples the loader
serves as ref, finds peak position and peak/mean.
tb/tb_matched_filter_processing_chain.v: wait timeouts bumped
50000 -> 500000 cycles to accommodate production FFT pipeline.
MCU
main.cpp checkSystemHealthStatus: latch system_emergency_state on
the error_count > 10 path so the SAFE-MODE blink loop in main()
actually engages (was bypassed because predicate was false).
main.cpp: move FPGA reset BEFORE the if(PowerAmplifier) block so
adar_tr_x is driven LOW (RX commanded externally) before PA Vdd
reaches 22 V. Old reset block at the original location removed.
main.cpp MX_GPIO_Init: add GPIO_PIN_12 (FPGA reset) to the
explicit WritePin(LOW) list so the safe initial state is no
longer implicit.
main.cpp checkSystemHealth: rate-limit ADAR1000
verifyDeviceCommunication (HAL_Delay 1ms x 4 devices = 4 ms
blocking SPI burst per main-loop iteration) from every-loop to
every 2 s. readTemperature stays per-loop so over-temp
detection latency is unchanged.
USBHandler.cpp processSettingsData: dispatch threshold bumped
74 -> 82 (matches parser minimum); buffer drained after parse
attempt (slide remaining bytes left) so a false END find no
longer sticks the buffer until 256-byte overflow.
GUI
radar_protocol.py: NUM_RANGE_BINS 64 -> 512 (matches FPGA
RP_NUM_RANGE_BINS); NUM_CELLS 2048 -> 16384.
radar_protocol.py _ingest_sample: honor FPGA frame_start bit for
resync after a USB drop; capture range_profile[rbin] once per
range bin at dbin == 0 (FPGA emits the same range_i/range_q for
all 32 Doppler cells of a given range bin; previous accumulator
inflated the profile 32x).
v7/models.py RadarSettings: range_resolution 24 -> 6 m (matches
c/(2*100MHz)*4); max_distance and coverage_radius 1536 -> 3072 m;
map_size 2000 -> 4000.
v7/models.py WaveformConfig: n_range_bins 64 -> 512, fft_size
1024 -> 2048, decimation_factor 16 -> 4.
GUI_V65_Tk.py: _RANGE_PER_BIN math and stale "~24 m / ~1536 m"
comments updated.
test_v7.py: assertion values updated to match new defaults.
Tests
test_ddc_cosim_fuzz.py: remove unused os/tempfile imports, wrap
three long lines for ruff E501 compliance.
AERIS-10: Open Source Pulse Linear Frequency Modulated Phased Array Radar
AERIS-10 is an open-source, low-cost 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation. Available in two versions (3km and 20km range), it's designed for researchers, drone developers, and serious SDR enthusiasts who want to explore and experiment with phased array radar technology.
📡 Overview
The AERIS-10 project aims to democratize radar technology by providing a fully open-source, modular, and hackable radar system. Whether you're a university researcher, a drone startup, or an advanced maker, AERIS-10 offers a platform for experimenting with beamforming, pulse compression, Doppler processing, and target tracking.
🔬 Key Features
- Open Source Hardware & Software - Complete schematics, PCB layouts, firmware, and software available
- Dual Version Availability:
- AERIS-10N (Nexus): 3km range with 8x16 patch antenna array
- AERIS-10E (Extended): 20km range with 32x16 dielectric-filled slotted waveguide array
- Full Electronic Beam Steering - ±45° electronic steering in elevation and azimuth
- Advanced Signal Processing - On-board FPGA handles pulse compression, Doppler FFT, MTI, and CFAR
- Python GUI - User-friendly interface with map integration
- GPS/IMU Integration - Real-time position and attitude correction
- Modular Design - Separate power management, frequency synthesis, and RF boards
🏗️ System Architecture
Hardware Components
The AERIS-10 main sub-systems are:
-
Power Management Board - Supplies all necessary voltage levels to the electronics components with proper filtering and sequencing (sequencing ensured by the microcontroller)
-
Frequency Synthesizer Board - Uses a high-performance Low Jitter Clock Generator (AD9523-1) that supplies phase-aligned clock references for:
- RX and TX Frequency Synthesizers (ADF4382)
- DAC
- ADC
- FPGA
-
Main Board containing:
- DAC - Generates the RADAR Chirps
- 2x Microwave Mixers (LTC5552) - For up-conversion and IF-down-conversion
- 4x 4-Channel Phase Shifters (ADAR1000) - For RX and TX chain beamforming
- 16x Front End Chips (ADTR1107) - Used for both Low Noise Amplifying (RX) and Power Amplifying (TX) stages
- XC7A50T FPGA - Handles RADAR Signal Processing on the upstream FTG256 board:
- PLFM Chirps generation via the DAC
- Raw ADC data read
- Hybrid Automatic Gain Control (AGC) — cross-layer FPGA/STM32/GUI loop
- I/Q Baseband Down-Conversion
- Decimation
- Filtering
- Forward FFT
- Pulse Compression
- Doppler, MTI and CFAR processing
- USB Interface
- STM32F746xx Microcontroller - Used for:
- Power-up and power-down sequencing (see Power Management Excel File)
- FPGA communication
- Setup and Interface with:
- Clock Generator (AD9523-1)
- 2x Frequency Synthesizers (ADF4382)
- 4x 4-Channel Phase Shifters (ADAR1000) for RADAR pulse sequencing
- 2x ADS7830 8-channel I²C ADCs (Main Board, U88 @ 0x48 / U89 @ 0x4A) for 16x Idq measurement, one per PA channel, each sensed through a 5 mΩ shunt on the PA board and an INA241A3 current-sense amplifier (x50) on the Main Board
- 2x DAC5578 8-channel I²C DACs (Main Board, U7 @ 0x48 / U69 @ 0x49) for 16x Vg control, one per PA channel; closed-loop calibrated at boot to the target Idq
- GPS module (UM982) for GUI map centering and per-detection position tagging
- GY-85 IMU for pitch/roll correction of target coordinates
- BMP180 Barometer
- Stepper Motor
- 1x ADS7830 8-channel I²C ADC (Main Board, U10) reading 8 thermistors for thermal monitoring; a single GPIO (EN_DIS_COOLING) switches the cooling fans on when any channel exceeds the threshold
- RF switches
-
16x Power Amplifier Boards - Used only for AERIS-10E version, featuring 10Watt QPA2962 GaN amplifier for extended range
-
Antenna Arrays:
- AERIS-10N (Nexus) - 8x16 patch antenna array
- AERIS-10X (Extended) - 32x16 dielectric-filled slotted waveguide antenna array
-
Miscellaneous Components:
- Slip-Ring
- Stepper Motor and drivers
- Cooling Fans
- Enclosure
Processing Pipeline
- Waveform Generation - DAC creates LFM chirps
- Up/Down Conversion - LTC5552 mixers handle frequency translation
- Beam Steering - ADAR1000 phase shifters control 16 elements
- Signal Processing (FPGA):
- Raw ADC data capture
- I/Q baseband down-conversion
- Decimation & filtering (CIC/FIR)
- Pulse compression
- Doppler FFT processing
- MTI & CFAR detection
- System Management (STM32):
- Power sequencing
- Peripheral configuration
- GPS/IMU integration
- Stepper motor control
- Visualization (Python GUI):
- Real-time target plotting
- Map integration
- Radar control interface
📊 Technical Specifications
| Parameter | AERIS-10N (Nexus) | AERIS-10X (Extended) |
|---|---|---|
| Frequency | 10.5 GHz | 10.5 GHz |
| Max Range | 3 km | 20 km |
| Antenna | 8x16 Patch Array | 32x16 Slotted Waveguide |
| Beam Steering | Electronic (±45°) | Electronic (±45°) |
| Mechanical Scan | 360° (stepper motor) | 360° (stepper motor) |
| Output Power | ~1W×16 | 10W×16 (GaN amplifier) |
| Processing | FPGA + STM32 | FPGA + STM32 |
🚀 Getting Started
🧹 Repository File Placement Policy
To keep the repository root clean and make artifacts easy to find, place generated files in the following locations:
- Published reports (tracked, GitHub Pages):
docs/- Example:
docs/AERIS_Simulation_Report_v2.pdf
- Example:
- Simulation-generated outputs (local, gitignored):
5_Simulations/generated/- Plots, scenario outputs, temporary analysis directories
- FPGA/Vivado generated artifacts (local, gitignored):
9_Firmware/9_2_FPGA/reports/- VCD/VVP dumps, temporary CSVs, local report snapshots
- Reusable FPGA automation scripts (tracked):
9_Firmware/9_2_FPGA/scripts/- TCL flows, helper scripts used by build/bring-up
Do not leave generated artifacts in the repository root.
Prerequisites
- Basic understanding of radar principles
- Experience with PCB assembly (for hardware build)
- Python 3.8+ for the GUI software
- FPGA development tools (Vivado) for signal processing modifications
Hardware Assembly
- Order PCBs: Production outputs are under
/4_Schematics and Boards Layout/4_7_Production Files - Source Components: BOM/CPL files are co-located under
/4_Schematics and Boards Layout/4_7_Production Files - Assembly: Use the schematics in
/4_Schematics and Boards Layout/4_6_Schematicstogether with the production outputs above; a standalone assembly guide is not currently tracked - Antenna: Choose appropriate array files for your target variant
- Enclosure: Mechanical drawings currently live in
/8_Utils/Mechanical_Drawings
📜 License
This project is open-source but uses different licenses for hardware and software to ensure proper legal coverage.
Hardware Documentation
The hardware design files—including:
- Schematics and PCB layouts (in
/4_Schematics and Boards Layout) - Bill of Materials (BOM) files
- Gerber files and manufacturing outputs
- Mechanical drawings and enclosure designs
are licensed under the CERN Open Hardware Licence Version 2 – Permissive (CERN-OHL-P) .
This is a hardware-specific license that:
- ✅ Clearly defines "Hardware," "Documentation," and "Products"
- ✅ Includes explicit patent protection for contributors and users
- ✅ Provides stronger liability limitations (important for high-power RF)
- ✅ Aligns with professional open-hardware standards (CERN, OSHWA)
You may use, modify, and sell products based on these designs, provided you:
- Maintain the original copyright notices
- Distribute any modified designs under the same license
- Make your modifications available in Source format
Software and Firmware
The software components—including:
- FPGA code (VHDL/Verilog in
/9_Firmware) - Microcontroller firmware (STM32)
- Python GUI and utilities
remain under the MIT License for maximum flexibility.
Full License Texts
- The complete CERN-OHL-P license text is in the
LICENSEfile - MIT license terms apply to software where not otherwise specified
Why This Change?
Originally, the entire project used the MIT license. The community (special thanks to gmaynez!) pointed out that MIT lacks legal protections needed for physical hardware. The switch to CERN-OHL-P ensures the project is properly protected while maintaining the same permissive spirit.
📚 Documentation
Comprehensive documentation is available in the /docs folder and served via GitHub Pages at https://NawfalMotii79.github.io/PLFM_RADAR/docs/:
🤝 Contributing
We welcome contributions! Please see our Contributing Guidelines for details on repo layout, branch workflow, and basic PR checks.
Areas where help is especially appreciated:
- RF Engineers: Review designs, optimize antenna performance
- FPGA Developers: Optimize signal processing pipeline
- Software Developers: Enhance Python GUI and SDK
- Beta Testers: University researchers, drone startups, advanced makers
📞 Contact & Collaboration
I welcome serious inquiries from researchers, engineers, and potential collaborators. However, due to the high volume of interest in this project, please understand that I cannot guarantee a response to every message.
- Technical questions or bug reports: Please open a GitHub issue so the whole community can benefit from the discussion.
- Collaboration, licensing, or business inquiries: 📧 nawfal.motii.33 [at] gmail [dot] com
💰 Sponsors
Star ⭐ this repository if you're interested in open-source radar technology!
Note: This is an active development project. Some features are still in progress. Check the issues page for known limitations and upcoming features.