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https://github.com/NawfalMotii79/PLFM_RADAR.git
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Jason
977434a5f6
The header had two claims that "valid samples arrive every ~4 cycles" at the FIR boundary. That is false in the production wiring: the CIC `_4x` decimator turns clk_400m into a 100 M-pulse-per-second stream, then cdc_adc_to_processing crosses that into clk_100m where dst_valid asserts every cycle in steady state. The 4:1 ratio applies between the two clock domains, not as further sub-sampling inside clk_100m. This matters because the 32-tap coefficients were designed for the 25 MSPS rate the wrong comment described, but the FIR is actually being driven at 100 MSPS. The cutoff sits 4x higher than intended; existing tests pass because the 36-bit accumulator silently wraps on large sustained inputs (see RX-NEW-3 in the project ledger). Comment-only commit. No RTL behaviour change. Any future DSP-saving rework — symmetric pre-adder, 4:1 fold, Xilinx FIR Compiler — needs a designer call on whether to redesign coefficients for 100 MSPS, add a real decimation stage to hit 25 MSPS, or keep the current accidental behaviour.