Jason 52a3497ea2 refactor(fpga): gen_chirp_mem sources sizing from radar_params.vh ...

A-3: gen_chirp_mem.py hardcoded 30 us / 0.5 us / 2048-pt / 2 segments,
duplicating the same numbers defined as RP_LONG_CHIRP_SAMPLES_3KM,
RP_SHORT_CHIRP_SAMPLES, RP_FFT_SIZE, RP_LONG_SEGMENTS_3KM in
radar_params.vh. A change on one side would silently desync the .mem
files from the RTL sample counts.

The script now parses radar_params.vh for integer RP_* macros and
derives chirp durations from LONG_CHIRP_SAMPLES / FS_SYS. Physical
baseband constants (CHIRP_BW, FS_SYS, SCALE) stay hardcoded since
they are chirp-design properties, not FPGA sizing.

Regenerated .mem files are byte-identical to pre-change output.
32/32 regression PASS.

2026-04-22 20:54:43 +05:45

..

real_data

review(cosim): fix stale comment and wrong docstring derivation

2026-04-16 11:07:56 +05:45

adc_dc.hex

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adc_multi_target.hex

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adc_noise_only.hex

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adc_sine_1mhz.hex

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adc_single_target.hex

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bb_mf_test_i.hex

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bb_mf_test_q.hex

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compare_dc.csv

fix: enforce strict ruff lint (17 rule sets) across entire repo

2026-04-12 14:21:03 +05:45

compare_doppler.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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compare_mf_chirp.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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compare_mf_dc.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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compare_mf_impulse.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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compare_mf_tone5.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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compare_mf.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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compare_multi_target.csv

…

compare_noise_only.csv

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compare_sine_1mhz.csv

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compare_single_target.csv

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compare.py

fix: enforce strict ruff lint (17 rule sets) across entire repo

2026-04-12 14:21:03 +05:45

doppler_golden_py_moving.csv

fix(fpga): pre-bringup RTL hardening + test-suite hardening

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doppler_golden_py_moving.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

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doppler_golden_py_stationary.csv

fix(fpga): pre-bringup RTL hardening + test-suite hardening

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doppler_golden_py_stationary.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

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doppler_golden_py_two_targets.csv

fix(fpga): pre-bringup RTL hardening + test-suite hardening

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doppler_golden_py_two_targets.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

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doppler_input_moving.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

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doppler_input_stationary.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

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doppler_input_two_targets.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

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fpga_model.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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gen_chirp_mem.py

refactor(fpga): gen_chirp_mem sources sizing from radar_params.vh

2026-04-22 20:54:43 +05:45

gen_doppler_golden.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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gen_mf_cosim_golden.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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gen_multiseg_golden.py

fix: enforce strict ruff lint (17 rule sets) across entire repo

2026-04-12 14:21:03 +05:45

mf_golden_py_chirp.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_dc.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_i_chirp.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_i_dc.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_i_impulse.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_i_tone5.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_impulse.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_q_chirp.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_q_dc.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_q_impulse.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_q_tone5.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_golden_py_tone5.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_ref_chirp_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_ref_chirp_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_ref_dc_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_dc_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_ref_impulse_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_impulse_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_tone5_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_tone5_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_sig_chirp_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_sig_chirp_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

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mf_sig_dc_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_dc_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_impulse_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_impulse_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_tone5_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_tone5_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

multiseg_golden_seg0_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg0_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg1_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg1_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg2_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg2_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg3_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg3_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_input_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_input_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg0_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg0_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg1_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg1_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg2_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg2_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg3_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg3_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_golden_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_golden_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_golden.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_input_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_input_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_ref_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_ref_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

radar_scene.py

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

ref_chirp_i.hex

…

ref_chirp_q.hex

…

rtl_bb_dc.csv

fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H

2026-04-18 20:34:52 +05:45

rtl_bb_multi_target.csv

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rtl_bb_noise_only.csv

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rtl_bb_sine_1mhz.csv

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rtl_bb_single_target.csv

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rtl_mf_chirp.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

rtl_mf_dc.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

rtl_mf_impulse.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

rtl_mf_tone5.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

scenario_info.txt

…

validate_mem_files.py

fix: enforce strict ruff lint (17 rule sets) across entire repo

2026-04-12 14:21:03 +05:45