Jason 52a3497ea2 refactor(fpga): gen_chirp_mem sources sizing from radar_params.vh ...

A-3: gen_chirp_mem.py hardcoded 30 us / 0.5 us / 2048-pt / 2 segments,
duplicating the same numbers defined as RP_LONG_CHIRP_SAMPLES_3KM,
RP_SHORT_CHIRP_SAMPLES, RP_FFT_SIZE, RP_LONG_SEGMENTS_3KM in
radar_params.vh. A change on one side would silently desync the .mem
files from the RTL sample counts.

The script now parses radar_params.vh for integer RP_* macros and
derives chirp durations from LONG_CHIRP_SAMPLES / FS_SYS. Physical
baseband constants (CHIRP_BW, FS_SYS, SCALE) stay hardcoded since
they are chirp-design properties, not FPGA sizing.

Regenerated .mem files are byte-identical to pre-change output.
32/32 regression PASS.

2026-04-22 20:54:43 +05:45

..

constraints

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

formal

fix(rtl,gui,cosim,formal): adapt surrounding files for dual 16-pt FFT (follow-up to PR #33)

2026-04-06 23:15:50 +03:00

scripts

Revert "fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin)"

2026-04-20 21:47:19 +05:45

tb

refactor(fpga): gen_chirp_mem sources sizing from radar_params.vh

2026-04-22 20:54:43 +05:45

.gitignore

chore(fpga): untrack TB-generated CSV, ignore a.out

2026-04-22 13:36:03 +05:45

ad9484_interface_400m.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

adc_clk_mmcm_integration.md

Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix

2026-03-19 22:59:46 +02:00

adc_clk_mmcm.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

cdc_modules.v

fix(pre-bringup): second-batch P1/P2/P3 audit findings

2026-04-20 14:28:22 +05:45

cfar_ca.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

chirp_memory_loader_param.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

cic_decimator_4x_enhanced.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

dac_interface_single.v

…

ddc_400m.v

fix(pre-bringup): second-batch P1/P2/P3 audit findings

2026-04-20 14:28:22 +05:45

ddc_input_interface.v

…

doppler_processor.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

edge_detector.v

…

fft_engine.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fft_twiddle_16.mem

Fix staggered-PRF Doppler processing with dual 16-point FFTs

2026-03-27 23:05:28 +02:00

fft_twiddle_1024.mem

…

fft_twiddle_2048.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fir_lowpass.v

fix(rtl): force FIR adder tree to fabric to free 30 DSPs for FFT butterfly on 50T

2026-04-07 14:45:47 +03:00

fpga_self_test.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

frequency_matched_filter.v

…

latency_buffer.v

…

long_chirp_lut.mem

…

long_chirp_seg0_i.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

long_chirp_seg0_q.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

long_chirp_seg1_i.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

long_chirp_seg1_q.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

matched_filter_multi_segment.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

matched_filter_processing_chain.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

mti_canceller.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

nco_400m_enhanced.v

fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H

2026-04-18 20:34:52 +05:45

plfm_chirp_controller.v

fix(fpga): TX range-mode awareness + clamp reserved host codes

2026-04-22 20:26:43 +05:45

radar_mode_controller.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

radar_params.vh

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

radar_receiver_final.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

radar_system_top_50t.v

Revert "fix(fpga): move IBUF+BUFIO+BUFR into 50T wrapper (same scope as pad)"

2026-04-20 21:47:19 +05:45

radar_system_top_te0712_dev.v

…

radar_system_top_te0713_dev.v

Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments

2026-03-19 16:47:59 +02:00

radar_system_top_te0713_umft601x_dev.v

feat(fpga): make FT2232H default USB interface, rewrite FT601 write FSM, add clock-loss watchdog

2026-04-16 16:18:52 +05:45

radar_system_top.v

fix(fpga): TX range-mode awareness + clamp reserved host codes

2026-04-22 20:26:43 +05:45

radar_transmitter.v

fix(fpga): TX range-mode awareness + clamp reserved host codes

2026-04-22 20:26:43 +05:45

range_bin_decimator.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

run_regression.sh

merge(wave2): manual resolution of 6 shared files — fft-2048 × p0 audit

2026-04-21 02:12:04 +05:45

rx_gain_control.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

short_chirp_i.mem

…

short_chirp_q.mem

…

usb_data_interface_ft2232h.v

merge(wave2): manual resolution of 6 shared files — fft-2048 × p0 audit

2026-04-21 02:12:04 +05:45

usb_data_interface.v

fix(fpga): correct USB frame-sync counter for 512x32 cell grid

2026-04-22 15:44:48 +05:45

xfft_16.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00