mirror of https://github.com/NawfalMotii79/PLFM_RADAR.git synced 2026-06-08 14:44:56 +00:00

T

Jason 4989c33aa6 PR-AB.b expanded commit 5: Beam-ready handshake (RTL + MCU + GUI)

Wire a per-frame MCU→FPGA "beam pattern ready" handshake so the chirp
scheduler can stall between 48-chirp frames until the MCU finishes
writing the next ADAR1000 pattern. The legacy unused stm32_new_chirp
input on PD8 is repurposed as stm32_beam_ready; chirp_scheduler.v gets
a new S_BEAM_WAIT state entered after each frame_pulse and an 80 ms
watchdog so a missed MCU toggle degrades to wall-clock cadence with a
sticky telemetry bit rather than stalling the radar.

Cold-reset defaults the handshake off (host_handshake_enable=0, new
opcode 0x1A); the GUI opts in once the MCU PD8 wiring is verified on
the bench. Both the FT601 and FT2232H status word 4 paths get the new
beam_handshake_watchdog_fired sticky at bit [1] (reclaimed from the
range_mode retirement in commit 1).

RTL:
- chirp_scheduler.v: 2-FF ASYNC_REG sync on beam_ready_async; 1-cycle
  edge detect (any transition, MCU side uses HAL_GPIO_TogglePin); new
  S_BEAM_WAIT state entered at frame_pulse when host_handshake_enable=1;
  23-bit beam_watchdog counter with BEAM_WATCHDOG_MAX = 8_000_000 (~80 ms
  at 100 MHz, ~10 nominal frames); beam_handshake_watchdog_fired output
  sticky across mixers_enable cycles, cleared only by reset_n; mid-wait
  disable releases the FSM so dropping the opcode never strands the
  radar between frames.
- radar_receiver_final.v: thread stm32_beam_ready_async +
  host_handshake_enable + beam_handshake_watchdog_fired through the
  scheduler instance.
- radar_system_top.v: rename input port stm32_new_chirp → stm32_beam_ready;
  add host_handshake_enable register (cold-reset = 1'b0); opcode 0x1A
  dispatch (value[0]); add rx_beam_handshake_watchdog wire; pack into
  status_words[4][1] in both USB paths.
- radar_system_top_50t.v: rename wrapper port + sub-instance wiring.
- usb_data_interface.v + usb_data_interface_ft2232h.v: add
  status_beam_handshake_watchdog input + 2-FF level CDC (same convention
  as F-6.4 / F-1.2 stickies); refresh word-4 layout doc comment; pack
  beam_handshake_wd_sync_1 into status_words[4][1].

XDC:
- xc7a50t_ftg256.xdc + xc7a200t_fbg484.xdc: rename stm32_new_chirp port
  references to stm32_beam_ready (same PD8 pin, F13 on 50T / L18 on
  200T).

MCU:
- main.h: add FPGA_BEAM_READY_Pin = GPIO_PIN_8 + FPGA_BEAM_READY_GPIO_Port
  = GPIOD alongside the existing FPGA_FRAME_PULSE alias.
- main.cpp:runRadarPulseSequence: insert HAL_GPIO_TogglePin(GPIOD,
  GPIO_PIN_8) after each setCustomBeamPattern16(RX) — once after the
  per-azimuth broadside (vector_0), once after matrix1, once after
  matrix2 — between the SPI burst completion and waitForFramePulse.

GUI:
- radar_protocol.py: Opcode.HANDSHAKE_ENABLE = 0x1A;
  StatusResponse.beam_handshake_watchdog = 0 default; parse word 4 bit
  [1] in parse_status_packet; update word-4 layout comment.
- test_GUI_V65_Tk.py: add beam_handshake_watchdog kwarg to
  _make_status_packet (sets bit [1] of word 4); refresh
  test_parse_status_word4_layout_co_spec to cover the new bit (used+9=32);
  add test_parse_status_beam_handshake_watchdog round-trip;
  test_handshake_enable_opcode pins 0x1A; defaults / chirps_mismatch /
  agc-coexist tests gain a watchdog==0 assertion; bump
  test_all_rtl_opcodes_present expected set to include 0x17/0x18/0x19/0x1A.

TB:
- new tb_chirp_scheduler_handshake.v (16 checks): legacy open-loop, edge
  exit (rising + falling), 200-cycle idle hold, watchdog auto-advance
  via force on dut.beam_watchdog, sticky-survives-mixers_disable,
  mid-wait disable release, reset_n clears sticky.
- run_regression.sh: register the new TB in PHASE 1.
- tb_radar_receiver_final.v: tie the 3 new receiver ports off
  (beam_ready_async=0, handshake_enable=0, watchdog unconnected).
- tb_system_mechanics.v / tb_system_opcodes.v: explicit
  .stm32_beam_ready(1'b0) connection (the cold-reset
  host_handshake_enable=0 keeps the FSM out of S_BEAM_WAIT).
- tb_usb_data_interface.v / tb_usb_protocol_v2.v / tb_e2e_dsp_to_host.v /
  tb_ft2232h_frame_drop.v: tie .status_beam_handshake_watchdog(1'b0).

Ride-along ruff sweep (14 → 0 across the repo):
- tb/cosim/compare_independent.py: RUF003 — '5×' → 'at least 5x'.
- tb/cosim/gen_e2e_expected.py: noqa: E402 on the post-sys.path import;
  drop unused EXPECTED_RANGE_BIN + EXPECTED_DOPPLER_BIN_PER_SF imports;
  fold the detect-class slot if/else into a ternary (SIM108).
- tb/cosim/gen_e2e_stimulus.py: drop int() wrapping round() at four
  call sites (RUF046 — round() already returns int in Python 3);
  rewrite the range-bin derivation comment block from code-like
  `# range_bin = ...` to prose (ERA001); strip stray f from
  placeholder-free error string (F541).
- tb/cosim/tb_e2e_dsp_to_host_parse.py: open(path, 'r') → open(path)
  (UP015).
- v7/dashboard.py: '3×' → '3x' (RUF003); drop quotes from
  'StatusResponse | None' annotation (UP037, file already has
  `from __future__ import annotations`).

CI summary (all suites green pre-commit):
- ruff: All checks passed!
- FPGA regression (iverilog): 43 / 0 / 0 (incl. new handshake TB 16/16).
- MCU tests: 51 / 0 + 34 / 0 + 13 / 13 ADAR1000_AGC.
- GUI Tk (test_GUI_V65_Tk): 120 / 0.
- GUI v7 (test_v7): 152 / 0.

Production rollout note: bitstream cold-resets with host_handshake_enable=0
so existing flashes keep their open-loop cadence until the GUI sends
opcode 0x1A=1. Once enabled, the per-pattern dwell tracks both the chirp
ladder (PD14 frame_pulse from commit-3 work) and the MCU pattern-write
completion (PD8 toggle from this commit), eliminating drift from the SPI
burst timing.

2026-05-11 12:07:08 +05:45

.github/workflows

chore(tests): retire v1 cross-layer iverilog cosim tier

2026-05-04 21:06:34 +05:45

1_Project_Description

Added ABAC INDUSTRY web site

2026-04-16 23:46:08 +01:00

2_Functional Diagram & Interconnection Matrices

Complete Diagram

2026-03-20 00:17:42 +00:00

3_Power Management

…

4_Schematics and Boards Layout

Add files via upload

2026-04-29 21:53:12 +01:00

5_Simulations

chore(sim): prune superseded antenna scripts — keep edge-fed-row v3 path

2026-05-05 10:47:04 +05:45

6_Application Notes

…

7_Components Datasheets and Application notes

…

8_Utils

Add Mechanical parts

2026-04-23 01:06:51 +01:00

9_Firmware

PR-AB.b expanded commit 5: Beam-ready handshake (RTL + MCU + GUI)

2026-05-11 12:07:08 +05:45

docs

docs(reports): replace AERIS_Antenna_Report.pdf with v2

2026-05-04 21:08:57 +05:45

.gitignore

chore(repo): PR-H — G-series close-out (regression infra + lint sweep)

2026-05-05 10:39:57 +05:45

CONTRIBUTING.md

docs(contributing): add AI usage policy section (closes #106 discussion)

2026-04-18 10:51:36 +03:00

Licence

…

pyproject.toml

chore(repo): PR-H — G-series close-out (regression infra + lint sweep)

2026-05-05 10:39:57 +05:45

README.md

Remove radar system image from README

2026-04-20 19:04:08 +01:00

uv.lock

chore(repo): PR-H — G-series close-out (regression infra + lint sweep)

2026-05-05 10:39:57 +05:45

README.md

AERIS-10: Open Source Pulse Linear Frequency Modulated Phased Array Radar

AERIS-10 is an open-source, low-cost 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation. Available in two versions (3km and 20km range), it's designed for researchers, drone developers, and serious SDR enthusiasts who want to explore and experiment with phased array radar technology.

📡 Overview

The AERIS-10 project aims to democratize radar technology by providing a fully open-source, modular, and hackable radar system. Whether you're a university researcher, a drone startup, or an advanced maker, AERIS-10 offers a platform for experimenting with beamforming, pulse compression, Doppler processing, and target tracking.

🔬 Key Features

Open Source Hardware & Software - Complete schematics, PCB layouts, firmware, and software available
Dual Version Availability:
- AERIS-10N (Nexus): 3km range with 8x16 patch antenna array
- AERIS-10E (Extended): 20km range with 32x16 dielectric-filled slotted waveguide array
Full Electronic Beam Steering - ±45° electronic steering in elevation and azimuth
Advanced Signal Processing - On-board FPGA handles pulse compression, Doppler FFT, MTI, and CFAR
Python GUI - User-friendly interface with map integration
GPS/IMU Integration - Real-time position and attitude correction
Modular Design - Separate power management, frequency synthesis, and RF boards

🏗️ System Architecture

Hardware Components

The AERIS-10 main sub-systems are:

Power Management Board - Supplies all necessary voltage levels to the electronics components with proper filtering and sequencing (sequencing ensured by the microcontroller)
Frequency Synthesizer Board - Uses a high-performance Low Jitter Clock Generator (AD9523-1) that supplies phase-aligned clock references for:
- RX and TX Frequency Synthesizers (ADF4382)
- DAC
- ADC
- FPGA
Main Board containing:
- DAC - Generates the RADAR Chirps
- 2x Microwave Mixers (LTC5552) - For up-conversion and IF-down-conversion
- 4x 4-Channel Phase Shifters (ADAR1000) - For RX and TX chain beamforming
- 16x Front End Chips (ADTR1107) - Used for both Low Noise Amplifying (RX) and Power Amplifying (TX) stages
- XC7A50T FPGA - Handles RADAR Signal Processing on the upstream FTG256 board:
  - PLFM Chirps generation via the DAC
  - Raw ADC data read
  - Hybrid Automatic Gain Control (AGC) — cross-layer FPGA/STM32/GUI loop
  - I/Q Baseband Down-Conversion
  - Decimation
  - Filtering
  - Forward FFT
  - Pulse Compression
  - Doppler, MTI and CFAR processing
  - USB Interface
- STM32F746xx Microcontroller - Used for:
  - Power-up and power-down sequencing (see Power Management Excel File)
  - FPGA communication
  - Setup and Interface with:
    - Clock Generator (AD9523-1)
    - 2x Frequency Synthesizers (ADF4382)
    - 4x 4-Channel Phase Shifters (ADAR1000) for RADAR pulse sequencing
    - 2x ADS7830 8-channel I²C ADCs (Main Board, U88 @ 0x48 / U89 @ 0x4A) for 16x Idq measurement, one per PA channel, each sensed through a 5 mΩ shunt on the PA board and an INA241A3 current-sense amplifier (x50) on the Main Board
    - 2x DAC5578 8-channel I²C DACs (Main Board, U7 @ 0x48 / U69 @ 0x49) for 16x Vg control, one per PA channel; closed-loop calibrated at boot to the target Idq
    - GPS module (UM982) for GUI map centering and per-detection position tagging
    - GY-85 IMU for pitch/roll correction of target coordinates
    - BMP180 Barometer
    - Stepper Motor
    - 1x ADS7830 8-channel I²C ADC (Main Board, U10) reading 8 thermistors for thermal monitoring; a single GPIO (EN_DIS_COOLING) switches the cooling fans on when any channel exceeds the threshold
    - RF switches
16x Power Amplifier Boards - Used only for AERIS-10E version, featuring 10Watt QPA2962 GaN amplifier for extended range
Antenna Arrays:
- AERIS-10N (Nexus) - 8x16 patch antenna array
- AERIS-10X (Extended) - 32x16 dielectric-filled slotted waveguide antenna array
Miscellaneous Components:
- Slip-Ring
- Stepper Motor and drivers
- Cooling Fans
- Enclosure

Processing Pipeline

Waveform Generation - DAC creates LFM chirps
Up/Down Conversion - LTC5552 mixers handle frequency translation
Beam Steering - ADAR1000 phase shifters control 16 elements
Signal Processing (FPGA):
- Raw ADC data capture
- I/Q baseband down-conversion
- Decimation & filtering (CIC/FIR)
- Pulse compression
- Doppler FFT processing
- MTI & CFAR detection
System Management (STM32):
- Power sequencing
- Peripheral configuration
- GPS/IMU integration
- Stepper motor control
Visualization (Python GUI):
- Real-time target plotting
- Map integration
- Radar control interface

📊 Technical Specifications

Parameter	AERIS-10N (Nexus)	AERIS-10X (Extended)
Frequency	10.5 GHz	10.5 GHz
Max Range	3 km	20 km
Antenna	8x16 Patch Array	32x16 Slotted Waveguide
Beam Steering	Electronic (±45°)	Electronic (±45°)
Mechanical Scan	360° (stepper motor)	360° (stepper motor)
Output Power	~1W×16	10W×16 (GaN amplifier)
Processing	FPGA + STM32	FPGA + STM32

🚀 Getting Started

🧹 Repository File Placement Policy

To keep the repository root clean and make artifacts easy to find, place generated files in the following locations:

Published reports (tracked, GitHub Pages): docs/
- Example: docs/AERIS_Simulation_Report_v2.pdf
Simulation-generated outputs (local, gitignored): 5_Simulations/generated/
- Plots, scenario outputs, temporary analysis directories
FPGA/Vivado generated artifacts (local, gitignored): 9_Firmware/9_2_FPGA/reports/
- VCD/VVP dumps, temporary CSVs, local report snapshots
Reusable FPGA automation scripts (tracked): 9_Firmware/9_2_FPGA/scripts/
- TCL flows, helper scripts used by build/bring-up

Do not leave generated artifacts in the repository root.

Prerequisites

Basic understanding of radar principles
Experience with PCB assembly (for hardware build)
Python 3.8+ for the GUI software
FPGA development tools (Vivado) for signal processing modifications

Hardware Assembly

Order PCBs: Production outputs are under /4_Schematics and Boards Layout/4_7_Production Files
Source Components: BOM/CPL files are co-located under /4_Schematics and Boards Layout/4_7_Production Files
Assembly: Use the schematics in /4_Schematics and Boards Layout/4_6_Schematics together with the production outputs above; a standalone assembly guide is not currently tracked
Antenna: Choose appropriate array files for your target variant
Enclosure: Mechanical drawings currently live in /8_Utils/Mechanical_Drawings

📜 License

This project is open-source but uses different licenses for hardware and software to ensure proper legal coverage.

Hardware Documentation

The hardware design files—including:

Schematics and PCB layouts (in /4_Schematics and Boards Layout)
Bill of Materials (BOM) files
Gerber files and manufacturing outputs
Mechanical drawings and enclosure designs

are licensed under the CERN Open Hardware Licence Version 2 – Permissive (CERN-OHL-P) .

This is a hardware-specific license that:

✅ Clearly defines "Hardware," "Documentation," and "Products"
✅ Includes explicit patent protection for contributors and users
✅ Provides stronger liability limitations (important for high-power RF)
✅ Aligns with professional open-hardware standards (CERN, OSHWA)

You may use, modify, and sell products based on these designs, provided you:

Maintain the original copyright notices
Distribute any modified designs under the same license
Make your modifications available in Source format

Software and Firmware

The software components—including:

FPGA code (VHDL/Verilog in /9_Firmware)
Microcontroller firmware (STM32)
Python GUI and utilities

remain under the MIT License for maximum flexibility.

Full License Texts

The complete CERN-OHL-P license text is in the LICENSE file
MIT license terms apply to software where not otherwise specified

Why This Change?

Originally, the entire project used the MIT license. The community (special thanks to gmaynez!) pointed out that MIT lacks legal protections needed for physical hardware. The switch to CERN-OHL-P ensures the project is properly protected while maintaining the same permissive spirit.

📚 Documentation

Comprehensive documentation is available in the /docs folder and served via GitHub Pages at https://NawfalMotii79.github.io/PLFM_RADAR/docs/:

🤝 Contributing

We welcome contributions! Please see our Contributing Guidelines for details on repo layout, branch workflow, and basic PR checks.

Areas where help is especially appreciated:

RF Engineers: Review designs, optimize antenna performance
FPGA Developers: Optimize signal processing pipeline
Software Developers: Enhance Python GUI and SDK
Beta Testers: University researchers, drone startups, advanced makers

📞 Contact & Collaboration

I welcome serious inquiries from researchers, engineers, and potential collaborators. However, due to the high volume of interest in this project, please understand that I cannot guarantee a response to every message.

Technical questions or bug reports: Please open a GitHub issue so the whole community can benefit from the discussion.
Collaboration, licensing, or business inquiries: 📧 nawfal.motii.33 [at] gmail [dot] com

💰 Sponsors

Star ⭐ this repository if you're interested in open-source radar technology!

Note: This is an active development project. Some features are still in progress. Check the issues page for known limitations and upcoming features.

Languages

PLSQL 32.8%

Verilog 18.6%

Python 15.6%

C 15.2%

SMT 9.2%

Other 8.6%

README.md Unescape Escape

AERIS-10: Open Source Pulse Linear Frequency Modulated Phased Array Radar

📡 Overview

🔬 Key Features

🏗️ System Architecture

Hardware Components

Processing Pipeline

📊 Technical Specifications

🚀 Getting Started

🧹 Repository File Placement Policy

Prerequisites

Hardware Assembly

📜 License

Hardware Documentation

Software and Firmware

Full License Texts

Why This Change?

📚 Documentation

🤝 Contributing

📞 Contact & Collaboration

💰 Sponsors

README.md