Jason 21aaa5ac33 fix(fpga): correct USB frame-sync counter for 512x32 cell grid ...

usb_data_interface.v NUM_CELLS was still 12'd2048 (64 range x 32 doppler)
from the pre-2048-FFT architecture. With 512 range bins x 32 Doppler, the
12-bit counter wrapped every 2048 packets and the host received 8 false
frame-start markers per real frame via the sample_counter==0 bit packed
into the detection byte. Widen counter to 15 bits and set NUM_CELLS to
16384. Sister file usb_data_interface_ft2232h.v was already correct.

Remove three stale testbenches hardcoded to the old 1024-pt / 64-bin
architecture (tb_mf_chain_synth, tb_fullchain_mti_cfar_realdata,
tb_range_fft_realdata). Equivalent current-architecture coverage already
exists in tb_matched_filter_processing_chain, tb_fullchain_realdata,
tb_fft_engine, tb_multiseg_cosim, and tb_mf_cosim.

2026-04-22 15:44:48 +05:45

..

9_1_Microcontroller

refactor(mcu): remove redundant ADAR1000 T/R SPI paths (FPGA-owned)

2026-04-21 01:09:38 +05:45

9_2_FPGA

fix(fpga): correct USB frame-sync counter for 512x32 cell grid

2026-04-22 15:44:48 +05:45

9_3_GUI

fix(gui): align radar parameters to FPGA truth (radar_scene.py)

2026-04-16 21:35:01 +05:45

tests/cross_layer

test(fpga): F-3.2 add DDC cosim fuzz runner with seed sweep

2026-04-20 15:48:34 +05:45

tools

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