Commit Graph
7 Commits
Author SHA1 Message Date
Serhii 96c1f68778 docs(readme): replace text disclaimer with WIP badge
Swap the verbose Alpha disclaimer paragraph for a simple
"Features: Work in Progress" badge next to the existing
Alpha badge, per review feedback from @JJassonn69.
Badge links to the issues page for current status.
2026-04-09 14:07:37 +03:00
Serhii 836243ab18 docs(readme): add Alpha disclaimer to Key Features
Core hardware works, but GPS/map integration, attitude correction,
and beam steering UI are not yet complete — callers deserve to know
before they build on those features.

Closes gap 10.5 from reality-check review.
2026-04-08 01:11:19 +03:00
Serhii 178484a72d Merge remote-tracking branch 'upstream/develop' 2026-04-08 01:10:48 +03:00
Serhii ab17d19df2 Merge remote-tracking branch 'origin/main' 2026-04-07 21:16:41 +03:00
Serhii ffc89f0bbd fix(rtl,gui,cosim,formal): adapt surrounding files for dual 16-pt FFT (follow-up to PR #33)
- radar_system_top.v: DC notch now masks to dop_bin[3:0] per sub-frame so both sub-frames get their DC zeroed correctly; rename DOPPLER_FFT_SIZE → DOPPLER_FRAME_CHIRPS to avoid confusion with the per-FFT size (now 16)
- radar_dashboard.py: remove fftshift (crosses sub-frame boundary), display raw Doppler bins, remove dead velocity constants
- golden_reference.py: model dual 16-pt FFT with per-sub-frame Hamming window, update DC notch and CFAR to match RTL
- fv_doppler_processor.sby: reference xfft_16.v / fft_twiddle_16.mem, raise BMC depth to 512 and cover to 1024
- fv_radar_mode_controller.sby: raise cover depth to 600
- fv_radar_mode_controller.v: pin cfg_* to reduced constants (documented as single-config proof), fix Property 5 mode guard, strengthen Cover 1
- STALE_NOTICE.md: document that real-data hex files are stale and need regeneration with external dataset

Closes #39
2026-04-06 23:15:50 +03:00
Serhii 48b3847256 fix(scripts): make Vivado TCL scripts portable and update RTL file lists
- Replace hardcoded /home/jason-stone/ paths with [info script]-relative
  path resolution in all 9 scripts (build17-21, insert_ila_probes,
  program_fpga, ila_capture, run_cdc_and_netlist)
- Point constraint references at tracked XDC files instead of
  untracked synth_only.xdc
- Remove six phantom RTL entries (chirp_lut_init.v, fft_1024_forward.v,
  fft_1024_inverse.v, level_shifter_interface.v, lvds_to_cmos_400m.v,
  usb_packet_analyzer.v)
- Add six existing modules to file lists (rx_gain_control.v,
  mti_canceller.v, cfar_ca.v, fpga_self_test.v, xfft_16.v,
  adc_clk_mmcm.v)

Closes #38
2026-04-06 22:53:42 +03:00
Serhii 7eb81668e0 docs: fix FPGA part number, dead paths, and add CONTRIBUTING.md
- README: XC7A100T → XC7A50T to match the XDC correction note
  (constraints/xc7a50t_ftg256.xdc lines 9-11)
- README: replace dead /10_docs/ paths with tracked locations
- README: update contributing section to reference CONTRIBUTING.md
- Add minimal CONTRIBUTING.md with repo layout and PR checklist

Closes #37
2026-04-06 20:06:56 +03:00