PR-AB.b expanded commit 3: XDC + MCU GPIO scrub (PD9 / PD10)

Strip the FPGA-side pin constraints and MCU-side GPIO init+toggles for
the two STM32→FPGA beam-step GPIOs that the commit 1 RTL strip rendered
unreachable. The MCU was toggling PD9 once per beam_pos iteration and
PD10 once per azimuth step; both edges fed FPGA edge_detector_enhanced
instances that drove elevation_counter / azimuth_counter regs in
plfm_chirp_controller_v2 — counters that were never consumed (status
pack didn't carry them; on 50T they went to _nc; on 200T to
unconstrained outputs). GUI already uses MCU-side software counters
m/n/y via USB-CDC.

- constraints/xc7a50t_ftg256.xdc: delete PACKAGE_PIN E16 (PD9) +
  D16 (PD10); tighten stm32_new_* wildcard to explicit stm32_new_chirp.
- constraints/xc7a200t_fbg484.xdc: delete PACKAGE_PIN N18 (PD9) +
  N19 (PD10); tighten wildcard same as 50T.
- main.cpp:633: delete HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_9) inside the
  matrix1/matrix2 beam_pos loop.
- main.cpp:655: delete HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_10) at the
  azimuth-step / stepper-rotate boundary.
- main.cpp:3118 (MX_GPIO_Init output level): drop PD9 + PD10 from the
  GPIOD WritePin OR-mask.
- main.cpp:3172-3174 (MX_GPIO_Init pin config): drop PD9 + PD10 from
  the GPIOD pin OR-mask + comment. PD9 + PD10 now default to high-Z
  inputs after MCU reset — no leakage path because the FPGA-side ports
  are gone.

MCU regression: 51/51 + 34/34 suites green. FPGA regression unchanged
at 42/0/0 (XDC isn't consumed by iverilog).

The remaining DIG_0..DIG_3 bus pins are PD8 stm32_new_chirp (kept until
commit 5 renames it to stm32_beam_ready), PD11 stm32_mixers_enable, and
PD12 reset_n.

9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc

@@ -230,13 +230,12 @@ set_property IOSTANDARD LVCMOS33 [get_ports {stm32_*_3v3}]
 # ============================================================================
 # Pin: L18 = IO_L16N_T2_A27_15
 set_property PACKAGE_PIN L18 [get_ports {stm32_new_chirp}]
-# Pin: N18 = IO_L17P_T2_A26_15
-set_property PACKAGE_PIN N18 [get_ports {stm32_new_elevation}]
-# Pin: N19 = IO_L17N_T2_A25_15
-set_property PACKAGE_PIN N19 [get_ports {stm32_new_azimuth}]
+# N18 / N19 retired in PR-AB.b expanded — formerly stm32_new_elevation /
+# stm32_new_azimuth. MCU side init is also stripped (see commit 3); the
+# pins default to high-Z inputs after MCU reset.
 # Pin: N20 = IO_L18P_T2_A24_15
 set_property PACKAGE_PIN N20 [get_ports {stm32_mixers_enable}]
-set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_*}]
+set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_chirp}]
 set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
 
 # ============================================================================

9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc

@@ -223,10 +223,11 @@ set_property IOSTANDARD LVCMOS18 [get_ports {stm32_*_1v8}]
 # DIG_5..DIG_7 are STM32 inputs (PD13-PD15) ← FPGA outputs (status / sync)
 
 set_property PACKAGE_PIN F13 [get_ports {stm32_new_chirp}]       ;# DIG_0 (PD8)
-set_property PACKAGE_PIN E16 [get_ports {stm32_new_elevation}]   ;# DIG_1 (PD9)
-set_property PACKAGE_PIN D16 [get_ports {stm32_new_azimuth}]     ;# DIG_2 (PD10)
+# DIG_1 (PD9) + DIG_2 (PD10) retired in PR-AB.b expanded — formerly
+# stm32_new_elevation / stm32_new_azimuth. MCU side init is also stripped
+# (see commit 3); the pins default to high-Z inputs after MCU reset.
 set_property PACKAGE_PIN F15 [get_ports {stm32_mixers_enable}]   ;# DIG_3 (PD11)
-set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_*}]
+set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_chirp}]
 set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
 # reset_n is DIG_4 (PD12) — constrained above in the RESET section