PR-AB.b expanded commit 3: XDC + MCU GPIO scrub (PD9 / PD10)

Strip the FPGA-side pin constraints and MCU-side GPIO init+toggles for
the two STM32→FPGA beam-step GPIOs that the commit 1 RTL strip rendered
unreachable. The MCU was toggling PD9 once per beam_pos iteration and
PD10 once per azimuth step; both edges fed FPGA edge_detector_enhanced
instances that drove elevation_counter / azimuth_counter regs in
plfm_chirp_controller_v2 — counters that were never consumed (status
pack didn't carry them; on 50T they went to _nc; on 200T to
unconstrained outputs). GUI already uses MCU-side software counters
m/n/y via USB-CDC.

- constraints/xc7a50t_ftg256.xdc: delete PACKAGE_PIN E16 (PD9) +
  D16 (PD10); tighten stm32_new_* wildcard to explicit stm32_new_chirp.
- constraints/xc7a200t_fbg484.xdc: delete PACKAGE_PIN N18 (PD9) +
  N19 (PD10); tighten wildcard same as 50T.
- main.cpp:633: delete HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_9) inside the
  matrix1/matrix2 beam_pos loop.
- main.cpp:655: delete HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_10) at the
  azimuth-step / stepper-rotate boundary.
- main.cpp:3118 (MX_GPIO_Init output level): drop PD9 + PD10 from the
  GPIOD WritePin OR-mask.
- main.cpp:3172-3174 (MX_GPIO_Init pin config): drop PD9 + PD10 from
  the GPIOD pin OR-mask + comment. PD9 + PD10 now default to high-Z
  inputs after MCU reset — no leakage path because the FPGA-side ports
  are gone.

MCU regression: 51/51 + 34/34 suites green. FPGA regression unchanged
at 42/0/0 (XDC isn't consumed by iverilog).

The remaining DIG_0..DIG_3 bus pins are PD8 stm32_new_chirp (kept until
commit 5 renames it to stm32_beam_ready), PD11 stm32_mixers_enable, and
PD12 reset_n.

9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp

@@ -630,7 +630,8 @@ void runRadarPulseSequence() {
     m += m_max/2;
 
     for(int beam_pos = 0; beam_pos < 15; beam_pos++) {
-    	HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_9);// new_elevation -- mode 2'b00 input only; no-op in production mode 2'b01 but harmless to keep
+    	// PD9 toggle (formerly new_elevation) retired in PR-AB.b expanded —
+    	// FPGA-side input port + counter were removed, so the toggle was a no-op.
     	DIAG("SYS", "Beam pos %d/15: patterns matrix1/matrix2", beam_pos);
         // Pattern 1: matrix1 (negative-θ scan, peak at -62°..-3°)
         adarManager.setCustomBeamPattern16(matrix1[beam_pos], ADAR1000Manager::BeamDirection::TX);
@@ -652,8 +653,8 @@ void runRadarPulseSequence() {
 
     }
 
-    HAL_GPIO_TogglePin(GPIOD,GPIO_PIN_10);//Tell FPGA that there is a new azimuth
-    DIAG("SYS", "Azimuth GPIO toggle (GPIOD pin 10), stepping motor");
+    // PD10 toggle (formerly new_azimuth) retired in PR-AB.b expanded — see PD9 note above.
+    DIAG("SYS", "Azimuth step, stepping motor");
 
     y++; if(y>y_max)y=1;
 	  //Rotate stepper to next y position
@@ -3115,7 +3116,8 @@ static void MX_GPIO_Init(void)
                           |EN_P_3V3_VDD_SW_Pin, GPIO_PIN_RESET);
 
   /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12
+  // PD9 + PD10 retired in PR-AB.b expanded (formerly new_elevation / new_azimuth).
+  HAL_GPIO_WritePin(GPIOD, GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12
                           |STEPPER_CW_P_Pin|STEPPER_CLK_P_Pin|EN_DIS_RFPA_VDD_Pin|EN_DIS_COOLING_Pin, GPIO_PIN_RESET);
 
   /*Configure GPIO pin Output Level */
@@ -3169,9 +3171,10 @@ static void MX_GPIO_Init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
   HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 
-  /*Configure GPIO pins : PD8 PD9 PD10 PD11 PD12
-                           STEPPER_CW_P_Pin STEPPER_CLK_P_Pin EN_DIS_RFPA_VDD_Pin EN_DIS_COOLING_Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12
+  /*Configure GPIO pins : PD8 PD11 PD12
+                           STEPPER_CW_P_Pin STEPPER_CLK_P_Pin EN_DIS_RFPA_VDD_Pin EN_DIS_COOLING_Pin
+                           (PD9 / PD10 retired in PR-AB.b expanded — default high-Z input) */
+  GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12
                           |STEPPER_CW_P_Pin|STEPPER_CLK_P_Pin|EN_DIS_RFPA_VDD_Pin|EN_DIS_COOLING_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;

9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc

@@ -230,13 +230,12 @@ set_property IOSTANDARD LVCMOS33 [get_ports {stm32_*_3v3}]
 # ============================================================================
 # Pin: L18 = IO_L16N_T2_A27_15
 set_property PACKAGE_PIN L18 [get_ports {stm32_new_chirp}]
-# Pin: N18 = IO_L17P_T2_A26_15
-set_property PACKAGE_PIN N18 [get_ports {stm32_new_elevation}]
-# Pin: N19 = IO_L17N_T2_A25_15
-set_property PACKAGE_PIN N19 [get_ports {stm32_new_azimuth}]
+# N18 / N19 retired in PR-AB.b expanded — formerly stm32_new_elevation /
+# stm32_new_azimuth. MCU side init is also stripped (see commit 3); the
+# pins default to high-Z inputs after MCU reset.
 # Pin: N20 = IO_L18P_T2_A24_15
 set_property PACKAGE_PIN N20 [get_ports {stm32_mixers_enable}]
-set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_*}]
+set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_chirp}]
 set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
 
 # ============================================================================

9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc

@@ -223,10 +223,11 @@ set_property IOSTANDARD LVCMOS18 [get_ports {stm32_*_1v8}]
 # DIG_5..DIG_7 are STM32 inputs (PD13-PD15) ← FPGA outputs (status / sync)
 
 set_property PACKAGE_PIN F13 [get_ports {stm32_new_chirp}]       ;# DIG_0 (PD8)
-set_property PACKAGE_PIN E16 [get_ports {stm32_new_elevation}]   ;# DIG_1 (PD9)
-set_property PACKAGE_PIN D16 [get_ports {stm32_new_azimuth}]     ;# DIG_2 (PD10)
+# DIG_1 (PD9) + DIG_2 (PD10) retired in PR-AB.b expanded — formerly
+# stm32_new_elevation / stm32_new_azimuth. MCU side init is also stripped
+# (see commit 3); the pins default to high-Z inputs after MCU reset.
 set_property PACKAGE_PIN F15 [get_ports {stm32_mixers_enable}]   ;# DIG_3 (PD11)
-set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_*}]
+set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_chirp}]
 set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
 # reset_n is DIG_4 (PD12) — constrained above in the RESET section