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https://github.com/NawfalMotii79/PLFM_RADAR.git
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fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering
FPGA — RX chain
matched_filter_multi_segment.v: drop the gratuitous /4 scaling on
DDC sign-extended input (was ddc_i[17:2] + ddc_i[1]); use
ddc_i[15:0] directly. fft_engine has INTERNAL_W=32 with
saturating 16-bit output, so full 16-bit input is safe. Restores
~12 dB of MF input dynamic range.
radar_receiver_final.v: remove latency_buffer (count-N-pulses-then-
prime FIFO that left frame 1 with all-zero ref). Replaced with
a single-FF alignment register on ref_i/ref_q that matches the
1-FF stage multi_segment ST_PROCESSING uses on adc_data.
Verified by tb/tb_rxb_fullchain_latency.v — autocorrelation peak
at bin 0 with peak/mean ~88x.
doppler_processor.v / mti_canceller.v / cfar_ca.v /
range_bin_decimator.v / radar_receiver_final.v / radar_system_top.v
/ usb_data_interface_ft2232h.v: switch port and parameter widths
from RP_NUM_RANGE_BINS / RP_RANGE_BIN_BITS (always 512 / 9-bit)
to RP_MAX_OUTPUT_BINS / RP_RANGE_BIN_WIDTH_MAX (auto-scales:
50T 512 / 9-bit, 200T 4096 / 12-bit). Unblocks 200T 20 km mode
at the RX module boundary; USB wire-protocol extension still
pending.
radar_receiver_final.v: doppler_frame_done_prev reset value 0 -> 1
to prevent false done pulse on cycle 1 when level signal is
HIGH at reset.
matched_filter_processing_chain.v: delete the broken `ifdef
SIMULATION inline behavioural FFT (482 lines removed). It
produced wrong-bin peaks and 100-1000x weak magnitudes. Chain
now uses production fft_engine.v + frequency_matched_filter.v
in both iverilog and Vivado. Iverilog tests are ~38x slower per
chain pass but produce correct results. Misleading "OK with
Xilinx IP" comments at three test sites updated since the FFT
is in-house, not an IP placeholder.
FPGA — testbenches
tb/tb_rxb_latency_measure.v (new): measures chain internal pipeline
depth (~2057 cycles, chirp-agnostic).
tb/tb_rxb_fullchain_latency.v (new): full-chain autocorrelation
verification — drives ddc with the same chirp samples the loader
serves as ref, finds peak position and peak/mean.
tb/tb_matched_filter_processing_chain.v: wait timeouts bumped
50000 -> 500000 cycles to accommodate production FFT pipeline.
MCU
main.cpp checkSystemHealthStatus: latch system_emergency_state on
the error_count > 10 path so the SAFE-MODE blink loop in main()
actually engages (was bypassed because predicate was false).
main.cpp: move FPGA reset BEFORE the if(PowerAmplifier) block so
adar_tr_x is driven LOW (RX commanded externally) before PA Vdd
reaches 22 V. Old reset block at the original location removed.
main.cpp MX_GPIO_Init: add GPIO_PIN_12 (FPGA reset) to the
explicit WritePin(LOW) list so the safe initial state is no
longer implicit.
main.cpp checkSystemHealth: rate-limit ADAR1000
verifyDeviceCommunication (HAL_Delay 1ms x 4 devices = 4 ms
blocking SPI burst per main-loop iteration) from every-loop to
every 2 s. readTemperature stays per-loop so over-temp
detection latency is unchanged.
USBHandler.cpp processSettingsData: dispatch threshold bumped
74 -> 82 (matches parser minimum); buffer drained after parse
attempt (slide remaining bytes left) so a false END find no
longer sticks the buffer until 256-byte overflow.
GUI
radar_protocol.py: NUM_RANGE_BINS 64 -> 512 (matches FPGA
RP_NUM_RANGE_BINS); NUM_CELLS 2048 -> 16384.
radar_protocol.py _ingest_sample: honor FPGA frame_start bit for
resync after a USB drop; capture range_profile[rbin] once per
range bin at dbin == 0 (FPGA emits the same range_i/range_q for
all 32 Doppler cells of a given range bin; previous accumulator
inflated the profile 32x).
v7/models.py RadarSettings: range_resolution 24 -> 6 m (matches
c/(2*100MHz)*4); max_distance and coverage_radius 1536 -> 3072 m;
map_size 2000 -> 4000.
v7/models.py WaveformConfig: n_range_bins 64 -> 512, fft_size
1024 -> 2048, decimation_factor 16 -> 4.
GUI_V65_Tk.py: _RANGE_PER_BIN math and stale "~24 m / ~1536 m"
comments updated.
test_v7.py: assertion values updated to match new defaults.
Tests
test_ddc_cosim_fuzz.py: remove unused os/tempfile imports, wrap
three long lines for ruff E501 compliance.
This commit is contained in:
@@ -66,8 +66,8 @@ class TestRadarSettings(unittest.TestCase):
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def test_defaults(self):
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s = _models().RadarSettings()
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self.assertEqual(s.system_frequency, 10.5e9)
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self.assertEqual(s.coverage_radius, 1536)
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self.assertEqual(s.max_distance, 1536)
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self.assertEqual(s.coverage_radius, 3072)
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self.assertEqual(s.max_distance, 3072)
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class TestGPSData(unittest.TestCase):
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@@ -430,17 +430,17 @@ class TestWaveformConfig(unittest.TestCase):
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self.assertEqual(wc.chirp_duration_s, 30e-6)
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self.assertEqual(wc.pri_s, 167e-6)
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self.assertEqual(wc.center_freq_hz, 10.5e9)
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self.assertEqual(wc.n_range_bins, 64)
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self.assertEqual(wc.n_range_bins, 512)
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self.assertEqual(wc.n_doppler_bins, 32)
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self.assertEqual(wc.chirps_per_subframe, 16)
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self.assertEqual(wc.fft_size, 1024)
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self.assertEqual(wc.decimation_factor, 16)
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self.assertEqual(wc.fft_size, 2048)
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self.assertEqual(wc.decimation_factor, 4)
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def test_range_resolution(self):
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"""range_resolution_m should be ~23.98 m/bin (matched filter, 100 MSPS)."""
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"""range_resolution_m should be ~6.0 m/bin (matched filter, 100 MSPS, decim 4)."""
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from v7.models import WaveformConfig
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wc = WaveformConfig()
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self.assertAlmostEqual(wc.range_resolution_m, 23.983, places=1)
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self.assertAlmostEqual(wc.range_resolution_m, 5.996, places=2)
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def test_velocity_resolution(self):
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"""velocity_resolution_mps should be ~5.34 m/s/bin (PRI=167us, 16 chirps)."""
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@@ -452,7 +452,7 @@ class TestWaveformConfig(unittest.TestCase):
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"""max_range_m = range_resolution * n_range_bins."""
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from v7.models import WaveformConfig
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wc = WaveformConfig()
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self.assertAlmostEqual(wc.max_range_m, wc.range_resolution_m * 64, places=1)
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self.assertAlmostEqual(wc.max_range_m, wc.range_resolution_m * 512, places=1)
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def test_max_velocity(self):
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"""max_velocity_mps = velocity_resolution * n_doppler_bins / 2."""
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@@ -927,9 +927,9 @@ class TestExtractTargetsFromFrame(unittest.TestCase):
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"""Detection at range bin 10 → range = 10 * range_resolution."""
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from v7.processing import extract_targets_from_frame
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frame = self._make_frame(det_cells=[(10, 16)]) # dbin=16 = center → vel=0
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targets = extract_targets_from_frame(frame, range_resolution=23.983)
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targets = extract_targets_from_frame(frame, range_resolution=5.996)
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self.assertEqual(len(targets), 1)
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self.assertAlmostEqual(targets[0].range, 10 * 23.983, places=1)
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self.assertAlmostEqual(targets[0].range, 10 * 5.996, places=1)
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self.assertAlmostEqual(targets[0].velocity, 0.0, places=2)
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def test_velocity_sign(self):
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