fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

FPGA — RX chain
  matched_filter_multi_segment.v: drop the gratuitous /4 scaling on
    DDC sign-extended input (was ddc_i[17:2] + ddc_i[1]); use
    ddc_i[15:0] directly. fft_engine has INTERNAL_W=32 with
    saturating 16-bit output, so full 16-bit input is safe. Restores
    ~12 dB of MF input dynamic range.
  radar_receiver_final.v: remove latency_buffer (count-N-pulses-then-
    prime FIFO that left frame 1 with all-zero ref). Replaced with
    a single-FF alignment register on ref_i/ref_q that matches the
    1-FF stage multi_segment ST_PROCESSING uses on adc_data.
    Verified by tb/tb_rxb_fullchain_latency.v — autocorrelation peak
    at bin 0 with peak/mean ~88x.
  doppler_processor.v / mti_canceller.v / cfar_ca.v /
    range_bin_decimator.v / radar_receiver_final.v / radar_system_top.v
    / usb_data_interface_ft2232h.v: switch port and parameter widths
    from RP_NUM_RANGE_BINS / RP_RANGE_BIN_BITS (always 512 / 9-bit)
    to RP_MAX_OUTPUT_BINS / RP_RANGE_BIN_WIDTH_MAX (auto-scales:
    50T 512 / 9-bit, 200T 4096 / 12-bit). Unblocks 200T 20 km mode
    at the RX module boundary; USB wire-protocol extension still
    pending.
  radar_receiver_final.v: doppler_frame_done_prev reset value 0 -> 1
    to prevent false done pulse on cycle 1 when level signal is
    HIGH at reset.
  matched_filter_processing_chain.v: delete the broken `ifdef
    SIMULATION inline behavioural FFT (482 lines removed). It
    produced wrong-bin peaks and 100-1000x weak magnitudes. Chain
    now uses production fft_engine.v + frequency_matched_filter.v
    in both iverilog and Vivado. Iverilog tests are ~38x slower per
    chain pass but produce correct results. Misleading "OK with
    Xilinx IP" comments at three test sites updated since the FFT
    is in-house, not an IP placeholder.

FPGA — testbenches
  tb/tb_rxb_latency_measure.v (new): measures chain internal pipeline
    depth (~2057 cycles, chirp-agnostic).
  tb/tb_rxb_fullchain_latency.v (new): full-chain autocorrelation
    verification — drives ddc with the same chirp samples the loader
    serves as ref, finds peak position and peak/mean.
  tb/tb_matched_filter_processing_chain.v: wait timeouts bumped
    50000 -> 500000 cycles to accommodate production FFT pipeline.

MCU
  main.cpp checkSystemHealthStatus: latch system_emergency_state on
    the error_count > 10 path so the SAFE-MODE blink loop in main()
    actually engages (was bypassed because predicate was false).
  main.cpp: move FPGA reset BEFORE the if(PowerAmplifier) block so
    adar_tr_x is driven LOW (RX commanded externally) before PA Vdd
    reaches 22 V. Old reset block at the original location removed.
  main.cpp MX_GPIO_Init: add GPIO_PIN_12 (FPGA reset) to the
    explicit WritePin(LOW) list so the safe initial state is no
    longer implicit.
  main.cpp checkSystemHealth: rate-limit ADAR1000
    verifyDeviceCommunication (HAL_Delay 1ms x 4 devices = 4 ms
    blocking SPI burst per main-loop iteration) from every-loop to
    every 2 s. readTemperature stays per-loop so over-temp
    detection latency is unchanged.
  USBHandler.cpp processSettingsData: dispatch threshold bumped
    74 -> 82 (matches parser minimum); buffer drained after parse
    attempt (slide remaining bytes left) so a false END find no
    longer sticks the buffer until 256-byte overflow.

GUI
  radar_protocol.py: NUM_RANGE_BINS 64 -> 512 (matches FPGA
    RP_NUM_RANGE_BINS); NUM_CELLS 2048 -> 16384.
  radar_protocol.py _ingest_sample: honor FPGA frame_start bit for
    resync after a USB drop; capture range_profile[rbin] once per
    range bin at dbin == 0 (FPGA emits the same range_i/range_q for
    all 32 Doppler cells of a given range bin; previous accumulator
    inflated the profile 32x).
  v7/models.py RadarSettings: range_resolution 24 -> 6 m (matches
    c/(2*100MHz)*4); max_distance and coverage_radius 1536 -> 3072 m;
    map_size 2000 -> 4000.
  v7/models.py WaveformConfig: n_range_bins 64 -> 512, fft_size
    1024 -> 2048, decimation_factor 16 -> 4.
  GUI_V65_Tk.py: _RANGE_PER_BIN math and stale "~24 m / ~1536 m"
    comments updated.
  test_v7.py: assertion values updated to match new defaults.

Tests
  test_ddc_cosim_fuzz.py: remove unused os/tempfile imports, wrap
    three long lines for ruff E501 compliance.

9_Firmware/9_3_GUI/radar_protocol.py

@@ -43,9 +43,9 @@ STATUS_HEADER_BYTE = 0xBB
 DATA_PACKET_SIZE = 11               # 1 + 4 + 2 + 2 + 1 + 1
 STATUS_PACKET_SIZE = 26              # 1 + 24 + 1
 
-NUM_RANGE_BINS = 64
+NUM_RANGE_BINS = 512
 NUM_DOPPLER_BINS = 32
-NUM_CELLS = NUM_RANGE_BINS * NUM_DOPPLER_BINS  # 2048
+NUM_CELLS = NUM_RANGE_BINS * NUM_DOPPLER_BINS  # 16384
 
 WATERFALL_DEPTH = 64
 
@@ -777,6 +777,13 @@ class RadarAcquisition(threading.Thread):
 
     def _ingest_sample(self, sample: dict):
         """Place sample into current frame and emit when complete."""
+        # [GUI-C2 FIX] Use FPGA frame_start bit as the authoritative sync token.
+        # If FPGA flags frame_start mid-stream (after a USB drop or any glitch),
+        # finalize whatever we have and re-align to bin (0, 0). Without this the
+        # count-only sync stays permanently misaligned after a single dropped byte.
+        if sample.get("frame_start", 0) and self._sample_idx > 0:
+            self._finalize_frame()  # resets _sample_idx to 0 and starts a new frame
+
         rbin = self._sample_idx // NUM_DOPPLER_BINS
         dbin = self._sample_idx % NUM_DOPPLER_BINS
 
@@ -788,12 +795,15 @@ class RadarAcquisition(threading.Thread):
             if sample.get("detection", 0):
                 self._frame.detections[rbin, dbin] = 1
                 self._frame.detection_count += 1
-            # Accumulate FPGA range profile data (matched-filter output)
-            # Each sample carries the range_i/range_q for this range bin.
-            # Accumulate magnitude across Doppler bins for the range profile.
-            ri = int(sample.get("range_i", 0))
-            rq = int(sample.get("range_q", 0))
-            self._frame.range_profile[rbin] += abs(ri) + abs(rq)
+            # [GUI-C4 FIX] FPGA emits the same range_i/range_q for all 32 Doppler
+            # bins of a given range bin (it's the matched-filter range output,
+            # repeated per Doppler cell). Accumulating across all 32 inflates
+            # the profile 32x. Capture once per range bin at the first Doppler
+            # cell instead.
+            if dbin == 0:
+                ri = int(sample.get("range_i", 0))
+                rq = int(sample.get("range_q", 0))
+                self._frame.range_profile[rbin] = abs(ri) + abs(rq)
 
         self._sample_idx += 1