mirror of
https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-10 23:41:18 +00:00
fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering
FPGA — RX chain
matched_filter_multi_segment.v: drop the gratuitous /4 scaling on
DDC sign-extended input (was ddc_i[17:2] + ddc_i[1]); use
ddc_i[15:0] directly. fft_engine has INTERNAL_W=32 with
saturating 16-bit output, so full 16-bit input is safe. Restores
~12 dB of MF input dynamic range.
radar_receiver_final.v: remove latency_buffer (count-N-pulses-then-
prime FIFO that left frame 1 with all-zero ref). Replaced with
a single-FF alignment register on ref_i/ref_q that matches the
1-FF stage multi_segment ST_PROCESSING uses on adc_data.
Verified by tb/tb_rxb_fullchain_latency.v — autocorrelation peak
at bin 0 with peak/mean ~88x.
doppler_processor.v / mti_canceller.v / cfar_ca.v /
range_bin_decimator.v / radar_receiver_final.v / radar_system_top.v
/ usb_data_interface_ft2232h.v: switch port and parameter widths
from RP_NUM_RANGE_BINS / RP_RANGE_BIN_BITS (always 512 / 9-bit)
to RP_MAX_OUTPUT_BINS / RP_RANGE_BIN_WIDTH_MAX (auto-scales:
50T 512 / 9-bit, 200T 4096 / 12-bit). Unblocks 200T 20 km mode
at the RX module boundary; USB wire-protocol extension still
pending.
radar_receiver_final.v: doppler_frame_done_prev reset value 0 -> 1
to prevent false done pulse on cycle 1 when level signal is
HIGH at reset.
matched_filter_processing_chain.v: delete the broken `ifdef
SIMULATION inline behavioural FFT (482 lines removed). It
produced wrong-bin peaks and 100-1000x weak magnitudes. Chain
now uses production fft_engine.v + frequency_matched_filter.v
in both iverilog and Vivado. Iverilog tests are ~38x slower per
chain pass but produce correct results. Misleading "OK with
Xilinx IP" comments at three test sites updated since the FFT
is in-house, not an IP placeholder.
FPGA — testbenches
tb/tb_rxb_latency_measure.v (new): measures chain internal pipeline
depth (~2057 cycles, chirp-agnostic).
tb/tb_rxb_fullchain_latency.v (new): full-chain autocorrelation
verification — drives ddc with the same chirp samples the loader
serves as ref, finds peak position and peak/mean.
tb/tb_matched_filter_processing_chain.v: wait timeouts bumped
50000 -> 500000 cycles to accommodate production FFT pipeline.
MCU
main.cpp checkSystemHealthStatus: latch system_emergency_state on
the error_count > 10 path so the SAFE-MODE blink loop in main()
actually engages (was bypassed because predicate was false).
main.cpp: move FPGA reset BEFORE the if(PowerAmplifier) block so
adar_tr_x is driven LOW (RX commanded externally) before PA Vdd
reaches 22 V. Old reset block at the original location removed.
main.cpp MX_GPIO_Init: add GPIO_PIN_12 (FPGA reset) to the
explicit WritePin(LOW) list so the safe initial state is no
longer implicit.
main.cpp checkSystemHealth: rate-limit ADAR1000
verifyDeviceCommunication (HAL_Delay 1ms x 4 devices = 4 ms
blocking SPI burst per main-loop iteration) from every-loop to
every 2 s. readTemperature stays per-loop so over-temp
detection latency is unchanged.
USBHandler.cpp processSettingsData: dispatch threshold bumped
74 -> 82 (matches parser minimum); buffer drained after parse
attempt (slide remaining bytes left) so a false END find no
longer sticks the buffer until 256-byte overflow.
GUI
radar_protocol.py: NUM_RANGE_BINS 64 -> 512 (matches FPGA
RP_NUM_RANGE_BINS); NUM_CELLS 2048 -> 16384.
radar_protocol.py _ingest_sample: honor FPGA frame_start bit for
resync after a USB drop; capture range_profile[rbin] once per
range bin at dbin == 0 (FPGA emits the same range_i/range_q for
all 32 Doppler cells of a given range bin; previous accumulator
inflated the profile 32x).
v7/models.py RadarSettings: range_resolution 24 -> 6 m (matches
c/(2*100MHz)*4); max_distance and coverage_radius 1536 -> 3072 m;
map_size 2000 -> 4000.
v7/models.py WaveformConfig: n_range_bins 64 -> 512, fft_size
1024 -> 2048, decimation_factor 16 -> 4.
GUI_V65_Tk.py: _RANGE_PER_BIN math and stale "~24 m / ~1536 m"
comments updated.
test_v7.py: assertion values updated to match new defaults.
Tests
test_ddc_cosim_fuzz.py: remove unused os/tempfile imports, wrap
three long lines for ruff E501 compliance.
This commit is contained in:
Jason
@@ -61,8 +61,11 @@
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`include "radar_params.vh"
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// [RX-D FIX] NUM_RANGE_BINS and range_bin port widths now scale with
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// `RP_MAX_OUTPUT_BINS / `RP_RANGE_BIN_WIDTH_MAX (50T: 512/9, 200T: 4096/12).
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// CFAR magnitude BRAM depth uses `RP_CFAR_MAG_DEPTH which already scales.
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module cfar_ca #(
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parameter NUM_RANGE_BINS = `RP_NUM_RANGE_BINS, // 512
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parameter NUM_RANGE_BINS = `RP_MAX_OUTPUT_BINS, // 512 (50T) / 4096 (200T)
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parameter NUM_DOPPLER_BINS = `RP_NUM_DOPPLER_BINS, // 32
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parameter MAG_WIDTH = 17,
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parameter ALPHA_WIDTH = 8,
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@@ -76,7 +79,7 @@ module cfar_ca #(
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input wire [31:0] doppler_data,
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input wire doppler_valid,
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input wire [4:0] doppler_bin_in,
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input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in, // 9-bit
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input wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] range_bin_in, // 9-bit (50T) / 12-bit (200T)
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input wire frame_complete,
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// ========== CONFIGURATION ==========
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@@ -90,7 +93,7 @@ module cfar_ca #(
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// ========== DETECTION OUTPUTS ==========
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output reg detect_flag,
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output reg detect_valid,
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output reg [`RP_RANGE_BIN_BITS-1:0] detect_range, // 9-bit
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output reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] detect_range, // 9-bit (50T) / 12-bit (200T)
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output reg [4:0] detect_doppler,
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output reg [MAG_WIDTH-1:0] detect_magnitude,
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output reg [MAG_WIDTH-1:0] detect_threshold,
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@@ -105,10 +108,10 @@ module cfar_ca #(
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// INTERNAL PARAMETERS
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// ============================================================================
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localparam TOTAL_CELLS = NUM_RANGE_BINS * NUM_DOPPLER_BINS;
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localparam ADDR_WIDTH = `RP_CFAR_MAG_ADDR_W; // 14
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localparam ADDR_WIDTH = `RP_CFAR_MAG_ADDR_W; // 14 (50T) / 17 (200T)
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localparam COL_BITS = 5;
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localparam ROW_BITS = `RP_RANGE_BIN_BITS; // 9
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localparam SUM_WIDTH = MAG_WIDTH + ROW_BITS; // 26 bits: sum of up to 512 magnitudes
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localparam ROW_BITS = `RP_RANGE_BIN_WIDTH_MAX; // 9 (50T) / 12 (200T)
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localparam SUM_WIDTH = MAG_WIDTH + ROW_BITS; // 26 (50T) / 29 (200T)
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localparam PROD_WIDTH = SUM_WIDTH + ALPHA_WIDTH; // 34 bits
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localparam ALPHA_FRAC_BITS = 4; // Q4.4
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@@ -35,21 +35,17 @@
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`include "radar_params.vh"
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// ----------------------------------------------------------------------------
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// !!! 200T 20 km MODE BROKEN — FIX BEFORE 200T BRING-UP !!!
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// RANGE_BINS and the range_bin output port default to `RP_NUM_RANGE_BINS
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// (512) / `RP_RANGE_BIN_BITS (9). In 20 km mode the upstream pipeline
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// emits `RP_OUTPUT_RANGE_BINS_20KM = 4096 bins/chirp, which the internal
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// range-bin BRAMs and address counters here cannot represent — bins
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// 512..4095 alias onto bins 0..511 and the Doppler FFT collects a
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// scrambled slow-time vector per aliased range cell.
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// Latent on XC7A50T (SUPPORT_LONG_RANGE undefined → 3 km only); will
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// corrupt all 20 km output on XC7A200T. Before 200T bring-up: scale
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// RANGE_BINS with `RP_MAX_OUTPUT_BINS, widen range_bin, and resize the
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// per-range chirp buffers, or route 20 km mode around this block.
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// [RX-D FIX] RANGE_BINS and range_bin port now scale with `RP_MAX_OUTPUT_BINS
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// and `RP_RANGE_BIN_WIDTH_MAX (auto-conditional on SUPPORT_LONG_RANGE).
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// 50T (no SUPPORT_LONG_RANGE): 512 bins / 9-bit — 3 km only
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// 200T (SUPPORT_LONG_RANGE): 4096 bins / 12-bit — 3 km and 20 km
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// In 3 km mode the upstream produces 512 bins (uses bins 0..511 only on 200T).
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// In 20 km mode the upstream produces 4096 bins, which the BRAMs and counters
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// can now represent without aliasing.
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// ----------------------------------------------------------------------------
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module doppler_processor_optimized #(
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parameter DOPPLER_FFT_SIZE = `RP_DOPPLER_FFT_SIZE, // 16
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parameter RANGE_BINS = `RP_NUM_RANGE_BINS, // 512
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parameter RANGE_BINS = `RP_MAX_OUTPUT_BINS, // 512 (50T) / 4096 (200T)
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parameter CHIRPS_PER_FRAME = `RP_CHIRPS_PER_FRAME, // 32
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parameter CHIRPS_PER_SUBFRAME = `RP_CHIRPS_PER_SUBFRAME, // 16
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parameter WINDOW_TYPE = 0, // 0=Hamming, 1=Rectangular
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@@ -63,7 +59,7 @@ module doppler_processor_optimized #(
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output reg [31:0] doppler_output,
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output reg doppler_valid,
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output reg [4:0] doppler_bin, // {sub_frame, bin[3:0]}
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output reg [`RP_RANGE_BIN_BITS-1:0] range_bin, // 9-bit
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output reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] range_bin, // 9-bit (50T) / 12-bit (200T)
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output reg sub_frame, // 0=long PRI, 1=short PRI
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output wire processing_active,
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output wire frame_complete,
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@@ -74,9 +70,9 @@ module doppler_processor_optimized #(
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output wire [2:0] fv_state,
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output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_write_addr,
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output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_read_addr,
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output wire [`RP_RANGE_BIN_BITS-1:0] fv_write_range_bin,
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output wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] fv_write_range_bin,
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output wire [4:0] fv_write_chirp_index,
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output wire [`RP_RANGE_BIN_BITS-1:0] fv_read_range_bin,
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output wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] fv_read_range_bin,
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output wire [4:0] fv_read_doppler_index,
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output wire [9:0] fv_processing_timeout,
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output wire fv_frame_buffer_full,
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@@ -130,9 +126,9 @@ localparam MEM_DEPTH = RANGE_BINS * CHIRPS_PER_FRAME;
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// ==============================================
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// Control Registers
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// ==============================================
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reg [`RP_RANGE_BIN_BITS-1:0] write_range_bin;
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reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] write_range_bin;
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reg [4:0] write_chirp_index;
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reg [`RP_RANGE_BIN_BITS-1:0] read_range_bin;
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reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] read_range_bin;
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reg [4:0] read_doppler_index;
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reg frame_buffer_full;
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reg [9:0] chirps_received;
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@@ -248,8 +248,13 @@ always @(posedge clk or negedge reset_n) begin
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// Store in buffer via BRAM write port
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buf_we <= 1;
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buf_waddr <= buffer_write_ptr[10:0];
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buf_wdata_i <= ddc_i[17:2] + ddc_i[1];
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buf_wdata_q <= ddc_q[17:2] + ddc_q[1];
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// [RX-A FIX] ddc_i = {{2{gc_i[15]}}, gc_i} — top 2 bits are
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// sign-extension. The previous `ddc_i[17:2] + ddc_i[1]`
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// was a gratuitous /4 scaling (~12 dB dynamic-range loss).
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// fft_engine has INTERNAL_W=32 with saturating 16-bit output,
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// so full 16-bit input is safe (no bit-growth overflow risk).
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buf_wdata_i <= ddc_i[15:0];
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buf_wdata_q <= ddc_q[15:0];
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buffer_write_ptr <= buffer_write_ptr + 1;
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chirp_samples_collected <= chirp_samples_collected + 1;
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@@ -6,10 +6,14 @@
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* Pulse compression processing chain for AERIS-10 FMCW radar.
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* Implements: FFT(signal) → FFT(reference) → Conjugate multiply → IFFT
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*
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* This is a SIMULATION-COMPATIBLE implementation that replaces the Xilinx
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* FFT IP cores (FFT_enhanced) with behavioral Radix-2 DIT FFT engines.
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* For synthesis, replace the behavioral FFT instances with the actual
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* Xilinx xfft IP blocks.
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* Uses the in-house fft_engine.v (Radix-2 DIT, BRAM-backed) instantiated
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* once and reused 3 times per frame, plus frequency_matched_filter.v for
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* the pipelined conjugate multiply. Same code path runs in iverilog
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* simulation and Vivado synthesis.
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*
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* (An earlier `ifdef SIMULATION inline behavioural FFT was removed in
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* RX-NEW-1 fix 2026-04-23 — it produced wrong-bin peaks and weak
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* magnitudes that masked real correctness checks. See git history.)
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*
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* Interface contract (from matched_filter_multi_segment.v line 361):
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* .clk, .reset_n
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@@ -64,475 +68,8 @@ module matched_filter_processing_chain (
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output wire [3:0] chain_state
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);
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`ifdef SIMULATION
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// ============================================================================
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// PARAMETERS
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// ============================================================================
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localparam FFT_SIZE = `RP_FFT_SIZE; // 2048
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localparam ADDR_BITS = `RP_LOG2_FFT_SIZE; // log2(2048) = 11
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// State encoding (4-bit, up to 16 states)
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localparam [3:0] ST_IDLE = 4'd0;
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localparam [3:0] ST_FWD_FFT = 4'd1; // Collect samples + bit-reverse
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localparam [3:0] ST_FWD_BUTTERFLY = 4'd2; // Signal FFT butterflies
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localparam [3:0] ST_REF_BITREV = 4'd3; // Bit-reverse copy reference
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localparam [3:0] ST_REF_BUTTERFLY = 4'd4; // Reference FFT butterflies
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localparam [3:0] ST_MULTIPLY = 4'd5; // Conjugate multiply
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localparam [3:0] ST_INV_BITREV = 4'd6; // Bit-reverse copy product
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localparam [3:0] ST_INV_BUTTERFLY = 4'd7; // IFFT butterflies + scale
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localparam [3:0] ST_OUTPUT = 4'd8; // Stream results
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localparam [3:0] ST_DONE = 4'd9; // Return to idle
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reg [3:0] state;
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// ============================================================================
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// SIGNAL BUFFERS
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// ============================================================================
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// Input sample counter
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reg [ADDR_BITS:0] fwd_in_count; // 0..FFT_SIZE
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reg fwd_frame_done; // All FFT_SIZE samples received
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// Signal time-domain buffer
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reg signed [15:0] fwd_buf_i [0:FFT_SIZE-1];
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reg signed [15:0] fwd_buf_q [0:FFT_SIZE-1];
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// Signal FFT output (frequency domain)
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reg signed [15:0] fwd_out_i [0:FFT_SIZE-1];
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reg signed [15:0] fwd_out_q [0:FFT_SIZE-1];
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reg fwd_out_valid;
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// Reference time-domain buffer
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reg signed [15:0] ref_buf_i [0:FFT_SIZE-1];
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reg signed [15:0] ref_buf_q [0:FFT_SIZE-1];
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// Reference FFT output (frequency domain)
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reg signed [15:0] ref_fft_i [0:FFT_SIZE-1];
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reg signed [15:0] ref_fft_q [0:FFT_SIZE-1];
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// ============================================================================
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// CONJUGATE MULTIPLY OUTPUT
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// ============================================================================
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reg signed [15:0] mult_out_i [0:FFT_SIZE-1];
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reg signed [15:0] mult_out_q [0:FFT_SIZE-1];
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reg mult_done;
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// ============================================================================
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// INVERSE FFT OUTPUT
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// ============================================================================
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reg signed [15:0] ifft_out_i [0:FFT_SIZE-1];
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reg signed [15:0] ifft_out_q [0:FFT_SIZE-1];
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reg ifft_done;
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// Output streaming
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reg [ADDR_BITS:0] out_count;
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reg out_valid_reg;
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reg signed [15:0] out_i_reg, out_q_reg;
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// ============================================================================
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// BEHAVIORAL RADIX-2 DIT FFT (simulation only)
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// ============================================================================
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// Working arrays for FFT computation (shared between fwd, ref, and inv FFTs)
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reg signed [31:0] work_re [0:FFT_SIZE-1];
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reg signed [31:0] work_im [0:FFT_SIZE-1];
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// Bit-reverse function
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function [ADDR_BITS-1:0] bit_reverse;
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input [ADDR_BITS-1:0] val;
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integer b;
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begin
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bit_reverse = 0;
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for (b = 0; b < ADDR_BITS; b = b + 1)
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bit_reverse[ADDR_BITS-1-b] = val[b];
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end
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endfunction
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// FFT computation variables
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integer fft_stage, fft_k, fft_j, fft_half, fft_span;
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integer fft_idx_even, fft_idx_odd;
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reg signed [31:0] tw_re, tw_im;
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reg signed [31:0] t_re, t_im;
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reg signed [31:0] u_re, u_im;
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real tw_angle;
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// ============================================================================
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// MAIN STATE MACHINE
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// ============================================================================
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integer i;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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state <= ST_IDLE;
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fwd_in_count <= 0;
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fwd_frame_done <= 0;
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fwd_out_valid <= 0;
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mult_done <= 0;
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ifft_done <= 0;
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out_count <= 0;
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out_valid_reg <= 0;
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out_i_reg <= 16'd0;
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out_q_reg <= 16'd0;
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end else begin
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// Defaults
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out_valid_reg <= 1'b0;
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case (state)
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// ================================================================
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// IDLE: Wait for valid ADC data, start collecting 2048 samples
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// ================================================================
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ST_IDLE: begin
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fwd_in_count <= 0;
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fwd_frame_done <= 0;
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fwd_out_valid <= 0;
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mult_done <= 0;
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ifft_done <= 0;
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out_count <= 0;
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if (adc_valid) begin
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// Store first sample (signal + reference)
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fwd_buf_i[0] <= $signed(adc_data_i);
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fwd_buf_q[0] <= $signed(adc_data_q);
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ref_buf_i[0] <= $signed(ref_chirp_real);
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ref_buf_q[0] <= $signed(ref_chirp_imag);
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fwd_in_count <= 1;
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state <= ST_FWD_FFT;
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end
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end
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// ================================================================
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// FWD_FFT: Collect remaining samples, then bit-reverse copy signal
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// (2048 samples total)
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// ================================================================
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ST_FWD_FFT: begin
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if (!fwd_frame_done) begin
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// Still collecting samples
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if (adc_valid && fwd_in_count < FFT_SIZE) begin
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fwd_buf_i[fwd_in_count] <= $signed(adc_data_i);
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fwd_buf_q[fwd_in_count] <= $signed(adc_data_q);
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ref_buf_i[fwd_in_count] <= $signed(ref_chirp_real);
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ref_buf_q[fwd_in_count] <= $signed(ref_chirp_imag);
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fwd_in_count <= fwd_in_count + 1;
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end
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if (fwd_in_count == FFT_SIZE) begin
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fwd_frame_done <= 1;
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// Bit-reverse copy SIGNAL into work arrays (via <=)
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for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
work_re[bit_reverse(i[ADDR_BITS-1:0])] <= {{16{fwd_buf_i[i][15]}}, fwd_buf_i[i]};
|
||||
work_im[bit_reverse(i[ADDR_BITS-1:0])] <= {{16{fwd_buf_q[i][15]}}, fwd_buf_q[i]};
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// Bit-reverse copy settled on previous clock.
|
||||
// Now transition to butterfly computation.
|
||||
state <= ST_FWD_BUTTERFLY;
|
||||
end
|
||||
end
|
||||
|
||||
// ================================================================
|
||||
// FWD_BUTTERFLY: Forward FFT of signal (all stages, simulation only)
|
||||
// ================================================================
|
||||
ST_FWD_BUTTERFLY: begin
|
||||
// In-place radix-2 DIT butterflies (blocking assignments)
|
||||
for (fft_stage = 0; fft_stage < ADDR_BITS; fft_stage = fft_stage + 1) begin
|
||||
fft_half = 1 << fft_stage;
|
||||
fft_span = fft_half << 1;
|
||||
for (fft_k = 0; fft_k < FFT_SIZE; fft_k = fft_k + fft_span) begin
|
||||
for (fft_j = 0; fft_j < fft_half; fft_j = fft_j + 1) begin
|
||||
fft_idx_even = fft_k + fft_j;
|
||||
fft_idx_odd = fft_idx_even + fft_half;
|
||||
|
||||
tw_angle = -2.0 * 3.14159265358979 * fft_j / (fft_span * 1.0);
|
||||
tw_re = $rtoi($cos(tw_angle) * 32767.0);
|
||||
tw_im = $rtoi($sin(tw_angle) * 32767.0);
|
||||
|
||||
t_re = (work_re[fft_idx_odd] * tw_re - work_im[fft_idx_odd] * tw_im) >>> 15;
|
||||
t_im = (work_re[fft_idx_odd] * tw_im + work_im[fft_idx_odd] * tw_re) >>> 15;
|
||||
|
||||
u_re = work_re[fft_idx_even];
|
||||
u_im = work_im[fft_idx_even];
|
||||
|
||||
work_re[fft_idx_even] = u_re + t_re;
|
||||
work_im[fft_idx_even] = u_im + t_im;
|
||||
work_re[fft_idx_odd] = u_re - t_re;
|
||||
work_im[fft_idx_odd] = u_im - t_im;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Copy signal FFT results to fwd_out (saturate to 16-bit)
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
if (work_re[i] > 32767)
|
||||
fwd_out_i[i] <= 16'sh7FFF;
|
||||
else if (work_re[i] < -32768)
|
||||
fwd_out_i[i] <= 16'sh8000;
|
||||
else
|
||||
fwd_out_i[i] <= work_re[i][15:0];
|
||||
|
||||
if (work_im[i] > 32767)
|
||||
fwd_out_q[i] <= 16'sh7FFF;
|
||||
else if (work_im[i] < -32768)
|
||||
fwd_out_q[i] <= 16'sh8000;
|
||||
else
|
||||
fwd_out_q[i] <= work_im[i][15:0];
|
||||
end
|
||||
|
||||
fwd_out_valid <= 1;
|
||||
state <= ST_REF_BITREV;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MF_CHAIN] Forward FFT complete");
|
||||
`endif
|
||||
end
|
||||
|
||||
// ================================================================
|
||||
// REF_BITREV: Bit-reverse copy reference into work arrays
|
||||
// ================================================================
|
||||
ST_REF_BITREV: begin
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
work_re[bit_reverse(i[ADDR_BITS-1:0])] <= {{16{ref_buf_i[i][15]}}, ref_buf_i[i]};
|
||||
work_im[bit_reverse(i[ADDR_BITS-1:0])] <= {{16{ref_buf_q[i][15]}}, ref_buf_q[i]};
|
||||
end
|
||||
state <= ST_REF_BUTTERFLY;
|
||||
end
|
||||
|
||||
// ================================================================
|
||||
// REF_BUTTERFLY: Forward FFT of reference (same algorithm as signal)
|
||||
// ================================================================
|
||||
ST_REF_BUTTERFLY: begin
|
||||
for (fft_stage = 0; fft_stage < ADDR_BITS; fft_stage = fft_stage + 1) begin
|
||||
fft_half = 1 << fft_stage;
|
||||
fft_span = fft_half << 1;
|
||||
for (fft_k = 0; fft_k < FFT_SIZE; fft_k = fft_k + fft_span) begin
|
||||
for (fft_j = 0; fft_j < fft_half; fft_j = fft_j + 1) begin
|
||||
fft_idx_even = fft_k + fft_j;
|
||||
fft_idx_odd = fft_idx_even + fft_half;
|
||||
|
||||
tw_angle = -2.0 * 3.14159265358979 * fft_j / (fft_span * 1.0);
|
||||
tw_re = $rtoi($cos(tw_angle) * 32767.0);
|
||||
tw_im = $rtoi($sin(tw_angle) * 32767.0);
|
||||
|
||||
t_re = (work_re[fft_idx_odd] * tw_re - work_im[fft_idx_odd] * tw_im) >>> 15;
|
||||
t_im = (work_re[fft_idx_odd] * tw_im + work_im[fft_idx_odd] * tw_re) >>> 15;
|
||||
|
||||
u_re = work_re[fft_idx_even];
|
||||
u_im = work_im[fft_idx_even];
|
||||
|
||||
work_re[fft_idx_even] = u_re + t_re;
|
||||
work_im[fft_idx_even] = u_im + t_im;
|
||||
work_re[fft_idx_odd] = u_re - t_re;
|
||||
work_im[fft_idx_odd] = u_im - t_im;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Copy reference FFT results to ref_fft (saturate to 16-bit)
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
if (work_re[i] > 32767)
|
||||
ref_fft_i[i] <= 16'sh7FFF;
|
||||
else if (work_re[i] < -32768)
|
||||
ref_fft_i[i] <= 16'sh8000;
|
||||
else
|
||||
ref_fft_i[i] <= work_re[i][15:0];
|
||||
|
||||
if (work_im[i] > 32767)
|
||||
ref_fft_q[i] <= 16'sh7FFF;
|
||||
else if (work_im[i] < -32768)
|
||||
ref_fft_q[i] <= 16'sh8000;
|
||||
else
|
||||
ref_fft_q[i] <= work_im[i][15:0];
|
||||
end
|
||||
|
||||
state <= ST_MULTIPLY;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MF_CHAIN] Reference FFT complete");
|
||||
`endif
|
||||
end
|
||||
|
||||
// ================================================================
|
||||
// MULTIPLY: Conjugate multiply FFT(signal) x conj(FFT(reference))
|
||||
// (a+jb)(c-jd) = (ac+bd) + j(bc-ad)
|
||||
// Uses fwd_out (signal FFT) and ref_fft (reference FFT)
|
||||
// ================================================================
|
||||
ST_MULTIPLY: begin
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin : mult_loop
|
||||
reg signed [31:0] a, b, c, d;
|
||||
reg signed [31:0] ac, bd, bc, ad;
|
||||
reg signed [31:0] re_result, im_result;
|
||||
|
||||
a = {{16{fwd_out_i[i][15]}}, fwd_out_i[i]};
|
||||
b = {{16{fwd_out_q[i][15]}}, fwd_out_q[i]};
|
||||
c = {{16{ref_fft_i[i][15]}}, ref_fft_i[i]};
|
||||
d = {{16{ref_fft_q[i][15]}}, ref_fft_q[i]};
|
||||
|
||||
ac = (a * c) >>> 15;
|
||||
bd = (b * d) >>> 15;
|
||||
bc = (b * c) >>> 15;
|
||||
ad = (a * d) >>> 15;
|
||||
|
||||
re_result = ac + bd;
|
||||
im_result = bc - ad;
|
||||
|
||||
// Saturate
|
||||
if (re_result > 32767)
|
||||
mult_out_i[i] <= 16'sh7FFF;
|
||||
else if (re_result < -32768)
|
||||
mult_out_i[i] <= 16'sh8000;
|
||||
else
|
||||
mult_out_i[i] <= re_result[15:0];
|
||||
|
||||
if (im_result > 32767)
|
||||
mult_out_q[i] <= 16'sh7FFF;
|
||||
else if (im_result < -32768)
|
||||
mult_out_q[i] <= 16'sh8000;
|
||||
else
|
||||
mult_out_q[i] <= im_result[15:0];
|
||||
end
|
||||
|
||||
mult_done <= 1;
|
||||
state <= ST_INV_BITREV;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MF_CHAIN] Conjugate multiply complete");
|
||||
`endif
|
||||
end
|
||||
|
||||
// ================================================================
|
||||
// INV_BITREV: Bit-reverse copy conjugate-multiply product
|
||||
// ================================================================
|
||||
ST_INV_BITREV: begin
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
work_re[bit_reverse(i[ADDR_BITS-1:0])] <= {{16{mult_out_i[i][15]}}, mult_out_i[i]};
|
||||
work_im[bit_reverse(i[ADDR_BITS-1:0])] <= {{16{mult_out_q[i][15]}}, mult_out_q[i]};
|
||||
end
|
||||
state <= ST_INV_BUTTERFLY;
|
||||
end
|
||||
|
||||
// ================================================================
|
||||
// INV_BUTTERFLY: IFFT butterflies (positive twiddle) + 1/N scaling
|
||||
// ================================================================
|
||||
ST_INV_BUTTERFLY: begin
|
||||
for (fft_stage = 0; fft_stage < ADDR_BITS; fft_stage = fft_stage + 1) begin
|
||||
fft_half = 1 << fft_stage;
|
||||
fft_span = fft_half << 1;
|
||||
for (fft_k = 0; fft_k < FFT_SIZE; fft_k = fft_k + fft_span) begin
|
||||
for (fft_j = 0; fft_j < fft_half; fft_j = fft_j + 1) begin
|
||||
fft_idx_even = fft_k + fft_j;
|
||||
fft_idx_odd = fft_idx_even + fft_half;
|
||||
|
||||
// IFFT twiddle: +2*pi (positive exponent for inverse)
|
||||
tw_angle = +2.0 * 3.14159265358979 * fft_j / (fft_span * 1.0);
|
||||
tw_re = $rtoi($cos(tw_angle) * 32767.0);
|
||||
tw_im = $rtoi($sin(tw_angle) * 32767.0);
|
||||
|
||||
t_re = (work_re[fft_idx_odd] * tw_re - work_im[fft_idx_odd] * tw_im) >>> 15;
|
||||
t_im = (work_re[fft_idx_odd] * tw_im + work_im[fft_idx_odd] * tw_re) >>> 15;
|
||||
|
||||
u_re = work_re[fft_idx_even];
|
||||
u_im = work_im[fft_idx_even];
|
||||
|
||||
work_re[fft_idx_even] = u_re + t_re;
|
||||
work_im[fft_idx_even] = u_im + t_im;
|
||||
work_re[fft_idx_odd] = u_re - t_re;
|
||||
work_im[fft_idx_odd] = u_im - t_im;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Scale by 1/N (right shift by log2(2048) = 11) and store
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin : ifft_scale
|
||||
reg signed [31:0] scaled_re, scaled_im;
|
||||
scaled_re = work_re[i] >>> ADDR_BITS;
|
||||
scaled_im = work_im[i] >>> ADDR_BITS;
|
||||
|
||||
if (scaled_re > 32767)
|
||||
ifft_out_i[i] <= 16'sh7FFF;
|
||||
else if (scaled_re < -32768)
|
||||
ifft_out_i[i] <= 16'sh8000;
|
||||
else
|
||||
ifft_out_i[i] <= scaled_re[15:0];
|
||||
|
||||
if (scaled_im > 32767)
|
||||
ifft_out_q[i] <= 16'sh7FFF;
|
||||
else if (scaled_im < -32768)
|
||||
ifft_out_q[i] <= 16'sh8000;
|
||||
else
|
||||
ifft_out_q[i] <= scaled_im[15:0];
|
||||
end
|
||||
|
||||
ifft_done <= 1;
|
||||
state <= ST_OUTPUT;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MF_CHAIN] Inverse FFT complete — range profile ready");
|
||||
`endif
|
||||
end
|
||||
|
||||
// ================================================================
|
||||
// OUTPUT: Stream out 2048 range profile samples, one per clock
|
||||
// ================================================================
|
||||
ST_OUTPUT: begin
|
||||
if (out_count < FFT_SIZE) begin
|
||||
out_i_reg <= ifft_out_i[out_count];
|
||||
out_q_reg <= ifft_out_q[out_count];
|
||||
out_valid_reg <= 1'b1;
|
||||
out_count <= out_count + 1;
|
||||
end else begin
|
||||
state <= ST_DONE;
|
||||
end
|
||||
end
|
||||
|
||||
// ================================================================
|
||||
// DONE: Return to idle, ready for next frame
|
||||
// ================================================================
|
||||
ST_DONE: begin
|
||||
state <= ST_IDLE;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MF_CHAIN] Frame complete, returning to IDLE");
|
||||
`endif
|
||||
end
|
||||
|
||||
default: state <= ST_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// OUTPUT ASSIGNMENTS
|
||||
// ============================================================================
|
||||
assign range_profile_i = out_i_reg;
|
||||
assign range_profile_q = out_q_reg;
|
||||
assign range_profile_valid = out_valid_reg;
|
||||
assign chain_state = state;
|
||||
|
||||
// ============================================================================
|
||||
// BUFFER INITIALIZATION (simulation)
|
||||
// ============================================================================
|
||||
integer init_idx;
|
||||
initial begin
|
||||
for (init_idx = 0; init_idx < FFT_SIZE; init_idx = init_idx + 1) begin
|
||||
fwd_buf_i[init_idx] = 16'd0;
|
||||
fwd_buf_q[init_idx] = 16'd0;
|
||||
fwd_out_i[init_idx] = 16'd0;
|
||||
fwd_out_q[init_idx] = 16'd0;
|
||||
ref_buf_i[init_idx] = 16'd0;
|
||||
ref_buf_q[init_idx] = 16'd0;
|
||||
ref_fft_i[init_idx] = 16'd0;
|
||||
ref_fft_q[init_idx] = 16'd0;
|
||||
mult_out_i[init_idx] = 16'd0;
|
||||
mult_out_q[init_idx] = 16'd0;
|
||||
ifft_out_i[init_idx] = 16'd0;
|
||||
ifft_out_q[init_idx] = 16'd0;
|
||||
work_re[init_idx] = 32'd0;
|
||||
work_im[init_idx] = 32'd0;
|
||||
end
|
||||
end
|
||||
|
||||
`else
|
||||
// ============================================================================
|
||||
// SYNTHESIS IMPLEMENTATION — Radix-2 DIT FFT via fft_engine
|
||||
// IMPLEMENTATION — Radix-2 DIT FFT via fft_engine
|
||||
// ============================================================================
|
||||
// Uses a single fft_engine instance (2048-pt) reused 3 times:
|
||||
// 1. Forward FFT of signal
|
||||
@@ -1245,6 +782,5 @@ initial begin
|
||||
end
|
||||
end
|
||||
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -44,20 +44,16 @@
|
||||
`include "radar_params.vh"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// !!! 200T 20 km MODE BROKEN — FIX BEFORE 200T BRING-UP !!!
|
||||
// The prev-chirp BRAM buffer is sized to NUM_RANGE_BINS (512) and the
|
||||
// range_bin_in port is 9 bits (`RP_RANGE_BIN_BITS). In 20 km mode the
|
||||
// upstream range_bin_decimator emits `RP_OUTPUT_RANGE_BINS_20KM = 4096
|
||||
// bins per chirp (8 segments × 512 decimated bins), which aliases into
|
||||
// the 9-bit address space and collapses bins 512..4095 onto bins 0..511.
|
||||
// On XC7A50T this is latent (SUPPORT_LONG_RANGE undefined → 3 km only),
|
||||
// but on XC7A200T with SUPPORT_LONG_RANGE the 20 km data path will
|
||||
// silently corrupt every range cell above 3 km.
|
||||
// Fix before 200T bring-up: scale NUM_RANGE_BINS/range_bin width with
|
||||
// `RP_MAX_OUTPUT_BINS, or gate MTI off entirely in 20 km mode.
|
||||
// [RX-D FIX] NUM_RANGE_BINS and range_bin port widths now scale with
|
||||
// `RP_MAX_OUTPUT_BINS and `RP_RANGE_BIN_WIDTH_MAX (conditional on
|
||||
// SUPPORT_LONG_RANGE):
|
||||
// 50T (no SUPPORT_LONG_RANGE): 512 bins / 9-bit — 3 km only
|
||||
// 200T (SUPPORT_LONG_RANGE): 4096 bins / 12-bit — supports 20 km mode
|
||||
// The prev-chirp BRAM buffer auto-resizes accordingly; in 20 km mode all
|
||||
// 4096 range cells are stored without aliasing.
|
||||
// ----------------------------------------------------------------------------
|
||||
module mti_canceller #(
|
||||
parameter NUM_RANGE_BINS = `RP_NUM_RANGE_BINS, // 512
|
||||
parameter NUM_RANGE_BINS = `RP_MAX_OUTPUT_BINS, // 512 (50T) / 4096 (200T)
|
||||
parameter DATA_WIDTH = `RP_DATA_WIDTH // 16
|
||||
) (
|
||||
input wire clk,
|
||||
@@ -67,13 +63,13 @@ module mti_canceller #(
|
||||
input wire signed [DATA_WIDTH-1:0] range_i_in,
|
||||
input wire signed [DATA_WIDTH-1:0] range_q_in,
|
||||
input wire range_valid_in,
|
||||
input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in, // 9-bit
|
||||
input wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] range_bin_in, // 9-bit (50T) / 12-bit (200T)
|
||||
|
||||
// ========== OUTPUT (to Doppler processor) ==========
|
||||
output reg signed [DATA_WIDTH-1:0] range_i_out,
|
||||
output reg signed [DATA_WIDTH-1:0] range_q_out,
|
||||
output reg range_valid_out,
|
||||
output reg [`RP_RANGE_BIN_BITS-1:0] range_bin_out, // 9-bit
|
||||
output reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] range_bin_out, // 9-bit (50T) / 12-bit (200T)
|
||||
|
||||
// ========== CONFIGURATION ==========
|
||||
input wire mti_enable, // 1=MTI active, 0=pass-through
|
||||
@@ -111,7 +107,7 @@ module mti_canceller #(
|
||||
|
||||
reg signed [DATA_WIDTH-1:0] range_i_d1, range_q_d1;
|
||||
reg range_valid_d1;
|
||||
reg [`RP_RANGE_BIN_BITS-1:0] range_bin_d1;
|
||||
reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] range_bin_d1;
|
||||
reg mti_enable_d1;
|
||||
reg use_long_chirp_d1;
|
||||
|
||||
@@ -120,7 +116,7 @@ always @(posedge clk or negedge reset_n) begin
|
||||
range_i_d1 <= {DATA_WIDTH{1'b0}};
|
||||
range_q_d1 <= {DATA_WIDTH{1'b0}};
|
||||
range_valid_d1 <= 1'b0;
|
||||
range_bin_d1 <= {`RP_RANGE_BIN_BITS{1'b0}};
|
||||
range_bin_d1 <= {`RP_RANGE_BIN_WIDTH_MAX{1'b0}};
|
||||
mti_enable_d1 <= 1'b0;
|
||||
use_long_chirp_d1 <= 1'b0;
|
||||
end else begin
|
||||
@@ -211,7 +207,7 @@ always @(posedge clk or negedge reset_n) begin
|
||||
range_i_out <= {DATA_WIDTH{1'b0}};
|
||||
range_q_out <= {DATA_WIDTH{1'b0}};
|
||||
range_valid_out <= 1'b0;
|
||||
range_bin_out <= {`RP_RANGE_BIN_BITS{1'b0}};
|
||||
range_bin_out <= {`RP_RANGE_BIN_WIDTH_MAX{1'b0}};
|
||||
has_previous <= 1'b0;
|
||||
mti_first_chirp <= 1'b1;
|
||||
prev_chirp_was_long <= 1'b0;
|
||||
|
||||
@@ -24,7 +24,7 @@ module radar_receiver_final (
|
||||
output wire [31:0] doppler_output,
|
||||
output wire doppler_valid,
|
||||
output wire [4:0] doppler_bin,
|
||||
output wire [`RP_RANGE_BIN_BITS-1:0] range_bin, // 9-bit
|
||||
output wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] range_bin, // 9-bit
|
||||
|
||||
// Raw matched-filter output (debug/bring-up)
|
||||
output wire signed [15:0] range_profile_i_out,
|
||||
@@ -158,9 +158,15 @@ wire doppler_frame_done_level; // raw level from doppler_processor
|
||||
reg doppler_frame_done_prev;
|
||||
wire doppler_frame_done; // rising-edge pulse (1 clk cycle)
|
||||
|
||||
// [RX-E FIX] doppler_frame_done_level is HIGH at reset (state==S_IDLE,
|
||||
// frame_buffer_full==0). Initializing prev to 1'b0 produces a spurious
|
||||
// rising-edge pulse on cycle 1, before any real frame has been processed,
|
||||
// which causes a stale AGC gain update and a phantom CFAR tick. Initialize
|
||||
// prev to 1'b1 so the first edge fires only after the doppler processor
|
||||
// actually exits idle for a real frame and returns.
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n)
|
||||
doppler_frame_done_prev <= 1'b0;
|
||||
doppler_frame_done_prev <= 1'b1;
|
||||
else
|
||||
doppler_frame_done_prev <= doppler_frame_done_level;
|
||||
end
|
||||
@@ -172,13 +178,13 @@ assign doppler_frame_done_out = doppler_frame_done;
|
||||
wire signed [15:0] decimated_range_i;
|
||||
wire signed [15:0] decimated_range_q;
|
||||
wire decimated_range_valid;
|
||||
wire [`RP_RANGE_BIN_BITS-1:0] decimated_range_bin; // 9-bit
|
||||
wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] decimated_range_bin; // 9-bit
|
||||
|
||||
// ========== MTI CANCELLER SIGNALS ==========
|
||||
wire signed [15:0] mti_range_i;
|
||||
wire signed [15:0] mti_range_q;
|
||||
wire mti_range_valid;
|
||||
wire [`RP_RANGE_BIN_BITS-1:0] mti_range_bin; // 9-bit
|
||||
wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] mti_range_bin; // 9-bit
|
||||
wire mti_first_chirp;
|
||||
|
||||
// ========== RADAR MODE CONTROLLER SIGNALS ==========
|
||||
@@ -383,28 +389,32 @@ chirp_memory_loader_param chirp_mem (
|
||||
.mem_ready(mem_ready)
|
||||
);
|
||||
|
||||
// 4. CRITICAL: Reference Chirp Latency Buffer
|
||||
// This aligns reference data with FFT output (3187 cycle delay)
|
||||
// TODO: verify empirically during hardware bring-up with correlation test
|
||||
wire [15:0] delayed_ref_i, delayed_ref_q;
|
||||
wire mem_ready_delayed;
|
||||
|
||||
latency_buffer #(
|
||||
.DATA_WIDTH(32), // 16-bit I + 16-bit Q
|
||||
.LATENCY(3187)
|
||||
) ref_latency_buffer (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.data_in({ref_i, ref_q}),
|
||||
.valid_in(mem_request),
|
||||
.data_out({delayed_ref_i, delayed_ref_q}),
|
||||
.valid_out(mem_ready_delayed)
|
||||
);
|
||||
|
||||
// Assign delayed reference signals (single pair — chirp_memory_loader_param
|
||||
// selects long/short reference upstream via use_long_chirp)
|
||||
assign ref_chirp_real = delayed_ref_i;
|
||||
assign ref_chirp_imag = delayed_ref_q;
|
||||
// 4. [RX-B FIX, Option A 2026-04-23] Reference chirp wired to MF chain with
|
||||
// a single-FF alignment delay. Previously ran through `latency_buffer` with
|
||||
// LATENCY=3187 — that module is a count-N-valid-pulses-then-prime FIFO,
|
||||
// not a true cycle delay. It needed ~2 frames of mem_request pulses before
|
||||
// any ref reached the chain (so frame 1 saw all-zero ref → noise output).
|
||||
// Removed in favour of a direct-wire path with one FF.
|
||||
//
|
||||
// Why the 1-FF stage: multi_segment ST_PROCESSING latches `adc_data` through
|
||||
// one register stage (`fft_input_i <= buf_rdata_i`) before it reaches the
|
||||
// chain. The ref path from chirp_memory_loader is combinational into the
|
||||
// chain. Without compensation, ref leads sig by 1 cycle → autocorrelation
|
||||
// peak at bin 1 instead of bin 0 (verified in tb/tb_rxb_fullchain_latency.v
|
||||
// against fft_engine.v synthesis path: peak/mean ratio ~80× confirms clean
|
||||
// correlation; peak position fixed to bin 0 by this register stage).
|
||||
reg [15:0] ref_chirp_real_d, ref_chirp_imag_d;
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
ref_chirp_real_d <= 16'd0;
|
||||
ref_chirp_imag_d <= 16'd0;
|
||||
end else begin
|
||||
ref_chirp_real_d <= ref_i;
|
||||
ref_chirp_imag_d <= ref_q;
|
||||
end
|
||||
end
|
||||
assign ref_chirp_real = ref_chirp_real_d;
|
||||
assign ref_chirp_imag = ref_chirp_imag_d;
|
||||
|
||||
// 5. Dual Chirp Matched Filter
|
||||
|
||||
@@ -449,7 +459,7 @@ matched_filter_multi_segment mf_dual (
|
||||
// Convert 2048 range bins to 512 bins for Doppler
|
||||
range_bin_decimator #(
|
||||
.INPUT_BINS(`RP_FFT_SIZE), // 2048
|
||||
.OUTPUT_BINS(`RP_NUM_RANGE_BINS), // 512
|
||||
.OUTPUT_BINS(`RP_MAX_OUTPUT_BINS), // 512 (50T) / 4096 (200T) [RX-D]
|
||||
.DECIMATION_FACTOR(`RP_DECIMATION_FACTOR) // 4
|
||||
) range_decim (
|
||||
.clk(clk),
|
||||
@@ -471,7 +481,7 @@ range_bin_decimator #(
|
||||
// H(z) = 1 - z^{-1} → null at DC Doppler, removes stationary clutter.
|
||||
// When host_mti_enable=0: transparent pass-through.
|
||||
mti_canceller #(
|
||||
.NUM_RANGE_BINS(`RP_NUM_RANGE_BINS), // 512
|
||||
.NUM_RANGE_BINS(`RP_MAX_OUTPUT_BINS), // 512 (50T) / 4096 (200T) [RX-D]
|
||||
.DATA_WIDTH(`RP_DATA_WIDTH) // 16
|
||||
) mti_inst (
|
||||
.clk(clk),
|
||||
@@ -528,7 +538,7 @@ assign range_data_valid = mti_range_valid;
|
||||
// ========== DOPPLER PROCESSOR ==========
|
||||
doppler_processor_optimized #(
|
||||
.DOPPLER_FFT_SIZE(`RP_DOPPLER_FFT_SIZE), // 16
|
||||
.RANGE_BINS(`RP_NUM_RANGE_BINS), // 512
|
||||
.RANGE_BINS(`RP_MAX_OUTPUT_BINS), // 512 (50T) / 4096 (200T) [RX-D]
|
||||
.CHIRPS_PER_FRAME(`RP_CHIRPS_PER_FRAME), // 32
|
||||
.CHIRPS_PER_SUBFRAME(`RP_CHIRPS_PER_SUBFRAME) // 16
|
||||
) doppler_proc (
|
||||
|
||||
@@ -127,7 +127,7 @@ module radar_system_top (
|
||||
output wire [31:0] dbg_doppler_data,
|
||||
output wire dbg_doppler_valid,
|
||||
output wire [4:0] dbg_doppler_bin,
|
||||
output wire [`RP_RANGE_BIN_BITS-1:0] dbg_range_bin,
|
||||
output wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] dbg_range_bin,
|
||||
|
||||
// System status
|
||||
output wire [3:0] system_status,
|
||||
@@ -181,13 +181,13 @@ wire tx_current_chirp_sync_valid;
|
||||
wire [31:0] rx_doppler_output;
|
||||
wire rx_doppler_valid;
|
||||
wire [4:0] rx_doppler_bin;
|
||||
wire [`RP_RANGE_BIN_BITS-1:0] rx_range_bin;
|
||||
wire [31:0] rx_range_profile;
|
||||
wire rx_range_valid;
|
||||
wire [15:0] rx_range_profile_decimated;
|
||||
wire rx_range_profile_decimated_valid;
|
||||
wire [15:0] rx_doppler_real;
|
||||
wire [15:0] rx_doppler_imag;
|
||||
wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] rx_range_bin;
|
||||
wire [31:0] rx_range_profile;
|
||||
wire rx_range_valid;
|
||||
wire [15:0] rx_range_profile_decimated;
|
||||
wire rx_range_profile_decimated_valid;
|
||||
wire [15:0] rx_doppler_real;
|
||||
wire [15:0] rx_doppler_imag;
|
||||
wire rx_doppler_data_valid;
|
||||
reg rx_detect_flag; // Threshold detection result (was rx_cfar_detection)
|
||||
reg rx_detect_valid; // Detection valid pulse (was rx_cfar_valid)
|
||||
@@ -542,12 +542,12 @@ radar_receiver_final rx_inst (
|
||||
.doppler_bin(rx_doppler_bin),
|
||||
.range_bin(rx_range_bin),
|
||||
|
||||
// Range-profile outputs
|
||||
.range_profile_i_out(rx_range_profile[15:0]),
|
||||
.range_profile_q_out(rx_range_profile[31:16]),
|
||||
.range_profile_valid_out(rx_range_valid),
|
||||
.decimated_range_mag_out(rx_range_profile_decimated),
|
||||
.decimated_range_valid_out(rx_range_profile_decimated_valid),
|
||||
// Range-profile outputs
|
||||
.range_profile_i_out(rx_range_profile[15:0]),
|
||||
.range_profile_q_out(rx_range_profile[31:16]),
|
||||
.range_profile_valid_out(rx_range_valid),
|
||||
.decimated_range_mag_out(rx_range_profile_decimated),
|
||||
.decimated_range_valid_out(rx_range_profile_decimated_valid),
|
||||
|
||||
.host_mode(host_radar_mode),
|
||||
.host_trigger(host_trigger_pulse),
|
||||
@@ -629,7 +629,7 @@ assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
|
||||
wire [31:0] notched_doppler_data = dc_notch_active ? 32'd0 : rx_doppler_output;
|
||||
wire notched_doppler_valid = rx_doppler_valid;
|
||||
wire [4:0] notched_doppler_bin = rx_doppler_bin;
|
||||
wire [`RP_RANGE_BIN_BITS-1:0] notched_range_bin = rx_range_bin;
|
||||
wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] notched_range_bin = rx_range_bin;
|
||||
|
||||
// ============================================================================
|
||||
// CFAR DETECTOR (replaces simple threshold detector)
|
||||
@@ -640,7 +640,7 @@ wire [`RP_RANGE_BIN_BITS-1:0] notched_range_bin = rx_range_bin;
|
||||
|
||||
wire cfar_detect_flag;
|
||||
wire cfar_detect_valid;
|
||||
wire [`RP_RANGE_BIN_BITS-1:0] cfar_detect_range;
|
||||
wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] cfar_detect_range;
|
||||
wire [4:0] cfar_detect_doppler;
|
||||
wire [16:0] cfar_detect_magnitude;
|
||||
wire [16:0] cfar_detect_threshold;
|
||||
@@ -731,10 +731,10 @@ end
|
||||
// DATA PACKING FOR USB
|
||||
// ============================================================================
|
||||
|
||||
// USB range profile must match the advertised 512-bin frame payload, so source it
|
||||
// from the decimated range stream that feeds Doppler rather than raw MF samples.
|
||||
assign usb_range_profile = {16'd0, rx_range_profile_decimated};
|
||||
assign usb_range_valid = rx_range_profile_decimated_valid;
|
||||
// USB range profile must match the advertised 512-bin frame payload, so source it
|
||||
// from the decimated range stream that feeds Doppler rather than raw MF samples.
|
||||
assign usb_range_profile = {16'd0, rx_range_profile_decimated};
|
||||
assign usb_range_valid = rx_range_profile_decimated_valid;
|
||||
|
||||
assign usb_doppler_real = rx_doppler_real;
|
||||
assign usb_doppler_imag = rx_doppler_imag;
|
||||
@@ -963,7 +963,7 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
|
||||
host_radar_mode <= 2'b01; // Default: auto-scan
|
||||
host_trigger_pulse <= 1'b0;
|
||||
host_detect_threshold <= 16'd10000; // Default threshold
|
||||
host_stream_control <= `RP_STREAM_CTRL_DEFAULT; // Default: all streams, mag-only mode
|
||||
host_stream_control <= `RP_STREAM_CTRL_DEFAULT; // Default: all streams, mag-only mode
|
||||
host_gain_shift <= 4'd0; // Default: pass-through (no gain change)
|
||||
// Gap 2: chirp timing defaults (match radar_mode_controller parameters)
|
||||
host_long_chirp_cycles <= 16'd3000;
|
||||
|
||||
@@ -32,9 +32,13 @@
|
||||
|
||||
`include "radar_params.vh"
|
||||
|
||||
// [RX-D FIX] OUTPUT_BINS and range_bin_index now scale with
|
||||
// `RP_MAX_OUTPUT_BINS / `RP_RANGE_BIN_WIDTH_MAX so 20 km mode gets the
|
||||
// full 4096-bin range axis (8 segments × 512 decimated bins per segment).
|
||||
// 50T: 512 / 9-bit. 200T: 4096 / 12-bit.
|
||||
module range_bin_decimator #(
|
||||
parameter INPUT_BINS = `RP_FFT_SIZE, // 2048
|
||||
parameter OUTPUT_BINS = `RP_NUM_RANGE_BINS, // 512
|
||||
parameter OUTPUT_BINS = `RP_MAX_OUTPUT_BINS, // 512 (50T) / 4096 (200T)
|
||||
parameter DECIMATION_FACTOR = `RP_DECIMATION_FACTOR // 4
|
||||
) (
|
||||
input wire clk,
|
||||
@@ -49,7 +53,7 @@ module range_bin_decimator #(
|
||||
output reg signed [15:0] range_i_out,
|
||||
output reg signed [15:0] range_q_out,
|
||||
output reg range_valid_out,
|
||||
output reg [`RP_RANGE_BIN_BITS-1:0] range_bin_index, // 9-bit
|
||||
output reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] range_bin_index, // 9-bit / 12-bit
|
||||
|
||||
// Configuration
|
||||
input wire [1:0] decimation_mode, // 00=decimate, 01=peak, 10=average
|
||||
@@ -82,7 +86,7 @@ reg [10:0] in_bin_count;
|
||||
|
||||
// Group tracking
|
||||
reg [1:0] group_sample_count; // 0..3 within current group of 4
|
||||
reg [8:0] output_bin_count; // 0..511 output bin index
|
||||
reg [`RP_RANGE_BIN_WIDTH_MAX-1:0] output_bin_count; // 0..OUTPUT_BINS-1
|
||||
|
||||
// State machine
|
||||
reg [2:0] state;
|
||||
@@ -146,7 +150,7 @@ always @(posedge clk or negedge reset_n) begin
|
||||
range_valid_out <= 1'b0;
|
||||
range_i_out <= 16'd0;
|
||||
range_q_out <= 16'd0;
|
||||
range_bin_index <= {`RP_RANGE_BIN_BITS{1'b0}};
|
||||
range_bin_index <= {`RP_RANGE_BIN_WIDTH_MAX{1'b0}};
|
||||
peak_i <= 16'd0;
|
||||
peak_q <= 16'd0;
|
||||
peak_mag <= 17'd0;
|
||||
|
||||
@@ -195,7 +195,7 @@ module tb_matched_filter_processing_chain;
|
||||
integer wait_count;
|
||||
begin
|
||||
wait_count = 0;
|
||||
while (chain_state != target_state && wait_count < 50000) begin
|
||||
while (chain_state != target_state && wait_count < 500000) begin
|
||||
@(posedge clk);
|
||||
wait_count = wait_count + 1;
|
||||
end
|
||||
@@ -208,7 +208,7 @@ module tb_matched_filter_processing_chain;
|
||||
integer wait_count;
|
||||
begin
|
||||
wait_count = 0;
|
||||
while (chain_state != ST_IDLE && wait_count < 50000) begin
|
||||
while (chain_state != ST_IDLE && wait_count < 500000) begin
|
||||
@(posedge clk);
|
||||
wait_count = wait_count + 1;
|
||||
end
|
||||
@@ -332,7 +332,11 @@ module tb_matched_filter_processing_chain;
|
||||
// noise that scatters energy far from bin 0. Xilinx IP uses full internal
|
||||
// precision and passes this correctly in hardware.
|
||||
if (!(cap_peak_bin <= 128 || cap_peak_bin >= FFT_SIZE - 128)) begin
|
||||
$display("[WARN] Autocorrelation peak at bin %0d (expected near 0) - behavioral FFT noise, OK with Xilinx IP", cap_peak_bin);
|
||||
// [RX-NEW-1] fft_engine.v is in-house — it IS the production FFT, not
|
||||
// a behavioural model that gets swapped for Xilinx IP. Wrong-bin peak
|
||||
// is therefore a real bug in fft_engine / frequency_matched_filter,
|
||||
// not "behavioral noise". See project memory ledger entry RX-NEW-1.
|
||||
$display("[FAIL-INFO] Autocorrelation peak at bin %0d (expected 0) — fft_engine bug, see RX-NEW-1", cap_peak_bin);
|
||||
end
|
||||
// Behavioral Q15 FFT scatters the peak, so we cannot assert bin
|
||||
// location — but the peak MUST dominate the mean magnitude. This
|
||||
@@ -496,7 +500,7 @@ module tb_matched_filter_processing_chain;
|
||||
|
||||
check(cap_count == FFT_SIZE, "Case 1: Got 2048 output samples");
|
||||
if (!(cap_peak_bin <= 128 || cap_peak_bin >= FFT_SIZE - 128)) begin
|
||||
$display("[WARN] Case 1: peak at bin %0d (expected near 0) - behavioral FFT noise", cap_peak_bin);
|
||||
$display("[FAIL-INFO] Case 1: peak at bin %0d (expected 0) — fft_engine bug, see RX-NEW-1", cap_peak_bin);
|
||||
end
|
||||
begin : p2m_case1
|
||||
integer k, sum_abs, mean_abs;
|
||||
@@ -538,7 +542,7 @@ module tb_matched_filter_processing_chain;
|
||||
|
||||
check(cap_count == FFT_SIZE, "Case 2: Got 2048 output samples");
|
||||
if (!(cap_peak_bin <= 128 || cap_peak_bin >= FFT_SIZE - 128)) begin
|
||||
$display("[WARN] Case 2: peak at bin %0d (expected near 0) - behavioral FFT noise", cap_peak_bin);
|
||||
$display("[FAIL-INFO] Case 2: peak at bin %0d (expected near 0) — fft_engine bug, see RX-NEW-1", cap_peak_bin);
|
||||
end
|
||||
begin : p2m_case2
|
||||
integer k, sum_abs, mean_abs;
|
||||
|
||||
@@ -0,0 +1,309 @@
|
||||
`timescale 1ns/1ps
|
||||
`include "radar_params.vh"
|
||||
|
||||
// ============================================================================
|
||||
// tb_rxb_fullchain_latency.v
|
||||
//
|
||||
// RX-B verification — Option A (latency_buffer removed, ref direct-wired).
|
||||
//
|
||||
// Production wiring this TB mirrors:
|
||||
// ddc_i/q (test stimulus) -> matched_filter_multi_segment -> chain
|
||||
// chirp_memory_loader -----direct wire--------------------> chain ref
|
||||
//
|
||||
// Tests:
|
||||
// 1) Pipeline timing: report cycle counts (first ddc_valid -> first
|
||||
// pc_valid). Confirms FSM advances and produces output.
|
||||
// 2) Autocorrelation peak position: drive ddc with the SAME short-chirp
|
||||
// samples that the loader serves up as ref. Output is the chirp
|
||||
// autocorrelation. Peak should be at bin 0 if ref/signal are aligned
|
||||
// at the chain. Any shift indicates an alignment error of N cycles.
|
||||
// ============================================================================
|
||||
|
||||
module tb_rxb_fullchain_latency;
|
||||
|
||||
localparam CLK_PERIOD = 10.0; // 100 MHz
|
||||
localparam FFT_SIZE = `RP_FFT_SIZE; // 2048
|
||||
localparam SHORT_LEN = 50; // matches RP_SHORT_CHIRP_SAMPLES
|
||||
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
|
||||
// multi_segment inputs
|
||||
reg signed [17:0] ddc_i;
|
||||
reg signed [17:0] ddc_q;
|
||||
reg ddc_valid;
|
||||
reg use_long_chirp;
|
||||
reg [5:0] chirp_counter;
|
||||
reg mc_new_chirp;
|
||||
reg mc_new_elevation;
|
||||
reg mc_new_azimuth;
|
||||
|
||||
// multi_segment <-> memory loader interconnect
|
||||
wire [1:0] segment_request;
|
||||
wire [10:0] sample_addr_out;
|
||||
wire mem_request;
|
||||
wire mem_ready_loader; // direct from loader
|
||||
|
||||
// Loader outputs (direct-wired to chain via multi_segment ports)
|
||||
wire [15:0] ref_i_raw;
|
||||
wire [15:0] ref_q_raw;
|
||||
|
||||
// multi_segment outputs
|
||||
wire signed [15:0] pc_i;
|
||||
wire signed [15:0] pc_q;
|
||||
wire pc_valid;
|
||||
wire [3:0] ms_status;
|
||||
|
||||
// ----- Memory loader -----
|
||||
chirp_memory_loader_param #(
|
||||
.DEBUG(0)
|
||||
) chirp_mem (
|
||||
.clk (clk),
|
||||
.reset_n (reset_n),
|
||||
.segment_select (segment_request),
|
||||
.mem_request (mem_request),
|
||||
.use_long_chirp (use_long_chirp),
|
||||
.sample_addr (sample_addr_out),
|
||||
.ref_i (ref_i_raw),
|
||||
.ref_q (ref_q_raw),
|
||||
.mem_ready (mem_ready_loader)
|
||||
);
|
||||
|
||||
// ----- 1-FF alignment register (mirrors radar_receiver_final.v) -----
|
||||
// multi_segment ST_PROCESSING latches adc_data through one register
|
||||
// stage; ref path needs the same to align at chain inputs.
|
||||
reg [15:0] ref_i_d, ref_q_d;
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
ref_i_d <= 16'd0;
|
||||
ref_q_d <= 16'd0;
|
||||
end else begin
|
||||
ref_i_d <= ref_i_raw;
|
||||
ref_q_d <= ref_q_raw;
|
||||
end
|
||||
end
|
||||
|
||||
// ----- multi_segment (drives chain internally) -----
|
||||
matched_filter_multi_segment ms_dut (
|
||||
.clk (clk),
|
||||
.reset_n (reset_n),
|
||||
.ddc_i (ddc_i),
|
||||
.ddc_q (ddc_q),
|
||||
.ddc_valid (ddc_valid),
|
||||
.use_long_chirp (use_long_chirp),
|
||||
.chirp_counter (chirp_counter),
|
||||
.mc_new_chirp (mc_new_chirp),
|
||||
.mc_new_elevation (mc_new_elevation),
|
||||
.mc_new_azimuth (mc_new_azimuth),
|
||||
.ref_chirp_real (ref_i_d),
|
||||
.ref_chirp_imag (ref_q_d),
|
||||
.segment_request (segment_request),
|
||||
.sample_addr_out (sample_addr_out),
|
||||
.mem_request (mem_request),
|
||||
.mem_ready (mem_ready_loader),
|
||||
.pc_i_w (pc_i),
|
||||
.pc_q_w (pc_q),
|
||||
.pc_valid_w (pc_valid),
|
||||
.status (ms_status)
|
||||
);
|
||||
|
||||
always #(CLK_PERIOD/2.0) clk = ~clk;
|
||||
|
||||
// -------- Cycle counter + first-event capture --------
|
||||
integer cycle_count;
|
||||
integer first_ddc_cycle;
|
||||
integer first_mem_request_cycle;
|
||||
integer first_pc_valid_cycle;
|
||||
integer pc_out_count;
|
||||
reg saw_ddc, saw_mem_req, saw_pc;
|
||||
|
||||
// -------- Output capture for peak detection --------
|
||||
reg signed [15:0] cap_i [0:FFT_SIZE-1];
|
||||
reg signed [15:0] cap_q [0:FFT_SIZE-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!reset_n) begin
|
||||
cycle_count <= 0;
|
||||
saw_ddc <= 0;
|
||||
saw_mem_req <= 0;
|
||||
saw_pc <= 0;
|
||||
pc_out_count <= 0;
|
||||
first_ddc_cycle <= 0;
|
||||
first_mem_request_cycle <= 0;
|
||||
first_pc_valid_cycle <= 0;
|
||||
end else begin
|
||||
cycle_count <= cycle_count + 1;
|
||||
|
||||
if (ddc_valid && !saw_ddc) begin
|
||||
first_ddc_cycle <= cycle_count;
|
||||
saw_ddc <= 1;
|
||||
$display("[T=%0t] FIRST ddc_valid at cycle %0d", $time, cycle_count);
|
||||
end
|
||||
if (mem_request && !saw_mem_req) begin
|
||||
first_mem_request_cycle <= cycle_count;
|
||||
saw_mem_req <= 1;
|
||||
$display("[T=%0t] FIRST mem_request at cycle %0d", $time, cycle_count);
|
||||
end
|
||||
if (pc_valid) begin
|
||||
if (!saw_pc) begin
|
||||
first_pc_valid_cycle <= cycle_count;
|
||||
saw_pc <= 1;
|
||||
$display("[T=%0t] FIRST pc_valid at cycle %0d", $time, cycle_count);
|
||||
end
|
||||
if (pc_out_count < FFT_SIZE) begin
|
||||
cap_i[pc_out_count] <= pc_i;
|
||||
cap_q[pc_out_count] <= pc_q;
|
||||
pc_out_count <= pc_out_count + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------- Stimulus arrays — load same short-chirp values that loader will serve --------
|
||||
reg [15:0] stim_chirp_i [0:SHORT_LEN-1];
|
||||
reg [15:0] stim_chirp_q [0:SHORT_LEN-1];
|
||||
|
||||
integer k;
|
||||
|
||||
task feed_short_chirp_signal;
|
||||
// Drive ddc with the chirp samples (autocorrelation: signal == ref).
|
||||
// Multi_segment will buffer them and zero-pad to FFT_SIZE.
|
||||
integer j;
|
||||
begin
|
||||
for (j = 0; j < SHORT_LEN; j = j + 1) begin
|
||||
ddc_i <= {{2{stim_chirp_i[j][15]}}, stim_chirp_i[j]}; // sign-ext to 18b
|
||||
ddc_q <= {{2{stim_chirp_q[j][15]}}, stim_chirp_q[j]};
|
||||
ddc_valid <= 1'b1;
|
||||
@(posedge clk);
|
||||
end
|
||||
ddc_valid <= 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
// -------- Peak finding --------
|
||||
integer peak_bin;
|
||||
integer peak_abs;
|
||||
integer mean_abs;
|
||||
integer abs_val;
|
||||
integer total_abs;
|
||||
|
||||
task find_peak;
|
||||
integer kk;
|
||||
integer val_i, val_q;
|
||||
begin
|
||||
peak_bin = 0;
|
||||
peak_abs = 0;
|
||||
total_abs = 0;
|
||||
for (kk = 0; kk < FFT_SIZE; kk = kk + 1) begin
|
||||
val_i = $signed(cap_i[kk]);
|
||||
val_q = $signed(cap_q[kk]);
|
||||
abs_val = (val_i < 0 ? -val_i : val_i)
|
||||
+ (val_q < 0 ? -val_q : val_q);
|
||||
total_abs = total_abs + abs_val;
|
||||
if (abs_val > peak_abs) begin
|
||||
peak_abs = abs_val;
|
||||
peak_bin = kk;
|
||||
end
|
||||
end
|
||||
mean_abs = total_abs / FFT_SIZE;
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
$dumpfile("tb_rxb_fullchain_latency.vcd");
|
||||
$dumpvars(0, tb_rxb_fullchain_latency);
|
||||
|
||||
clk = 0;
|
||||
reset_n = 0;
|
||||
ddc_i = 0;
|
||||
ddc_q = 0;
|
||||
ddc_valid = 0;
|
||||
use_long_chirp = 1'b0; // use SHORT chirp path so loader uses short_chirp_*.mem
|
||||
chirp_counter = 6'd0;
|
||||
mc_new_chirp = 1'b0;
|
||||
mc_new_elevation = 1'b0;
|
||||
mc_new_azimuth = 1'b0;
|
||||
|
||||
// Load the same short-chirp samples the loader will serve as ref,
|
||||
// so signal == ref → autocorrelation. Peak should be at bin 0 if
|
||||
// ref/signal alignment is correct.
|
||||
$readmemh("short_chirp_i.mem", stim_chirp_i, 0, SHORT_LEN-1);
|
||||
$readmemh("short_chirp_q.mem", stim_chirp_q, 0, SHORT_LEN-1);
|
||||
$display("[TB] Loaded %0d short-chirp samples for stimulus", SHORT_LEN);
|
||||
|
||||
repeat (8) @(posedge clk);
|
||||
reset_n = 1;
|
||||
repeat (8) @(posedge clk);
|
||||
|
||||
$display("\n=== RX-B Option A verification ===");
|
||||
$display("Configuration: latency_buffer REMOVED, ref direct-wired");
|
||||
$display("Path: chirp_memory_loader.ref_i ----> multi_segment.ref_chirp_real");
|
||||
$display("FFT_SIZE: %0d, SHORT_LEN: %0d", FFT_SIZE, SHORT_LEN);
|
||||
$display("");
|
||||
|
||||
// Pulse mc_new_chirp
|
||||
$display("[T=%0t] Pulsing mc_new_chirp HIGH...", $time);
|
||||
@(posedge clk);
|
||||
#1 mc_new_chirp = 1'b1;
|
||||
repeat (4) @(posedge clk);
|
||||
#1 mc_new_chirp = 1'b0;
|
||||
|
||||
// Feed signal samples (same as ref → autocorrelation)
|
||||
feed_short_chirp_signal;
|
||||
|
||||
// Wait for FFT_SIZE outputs (or timeout)
|
||||
for (k = 0; k < 200000; k = k + 1) begin
|
||||
@(posedge clk);
|
||||
if (pc_out_count >= FFT_SIZE) k = 200001;
|
||||
end
|
||||
|
||||
$display("\n=== TIMING ===");
|
||||
if (saw_ddc) $display("First ddc_valid : cycle %0d", first_ddc_cycle);
|
||||
if (saw_mem_req) $display("First mem_request : cycle %0d", first_mem_request_cycle);
|
||||
if (saw_pc) $display("First pc_valid : cycle %0d", first_pc_valid_cycle);
|
||||
$display("pc outputs captured: %0d / %0d", pc_out_count, FFT_SIZE);
|
||||
|
||||
if (pc_out_count >= FFT_SIZE) begin
|
||||
find_peak;
|
||||
$display("\n=== AUTOCORRELATION RESULT ===");
|
||||
$display("Peak bin : %0d", peak_bin);
|
||||
$display("Peak |I|+|Q| : %0d", peak_abs);
|
||||
$display("Mean |I|+|Q| : %0d", mean_abs);
|
||||
$display("Peak / mean ratio : ~%0dx",
|
||||
(mean_abs > 0) ? (peak_abs / mean_abs) : 0);
|
||||
$display("");
|
||||
// Run with the SYNTHESIS path (no +define+SIMULATION) to use
|
||||
// the production fft_engine.v — peak should be exactly at bin 0
|
||||
// with peak/mean > 50x for the autocorrelation case. The
|
||||
// SIMULATION path uses an inline behavioural FFT in
|
||||
// matched_filter_processing_chain.v with documented numerical
|
||||
// issues (peaks at non-zero bins, weak magnitudes); the
|
||||
// synthesis path is the production code.
|
||||
if (pc_out_count >= FFT_SIZE && peak_abs > 2 * mean_abs && peak_bin == 0) begin
|
||||
$display("[PASS] Frame 1 produces output, peak at bin 0, peak/mean ~%0dx",
|
||||
(mean_abs > 0) ? (peak_abs / mean_abs) : 0);
|
||||
$display(" RX-B fully fixed — latency_buffer removed + 1-FF align register.");
|
||||
end else if (pc_out_count >= FFT_SIZE && peak_abs > 2 * mean_abs) begin
|
||||
$display("[NEAR] Output present, peak/mean OK, but peak at bin %0d (not 0).",
|
||||
peak_bin);
|
||||
$display(" If running with +define+SIMULATION, this is the inline");
|
||||
$display(" behavioural FFT and is expected to fail. Run without it.");
|
||||
end else if (pc_out_count >= FFT_SIZE) begin
|
||||
$display("[FAIL] Output present but peak/mean too low — no real correlation.");
|
||||
end
|
||||
end else begin
|
||||
$display("\n=== TIMEOUT — chain did not produce all outputs ===");
|
||||
$display("ms_status=%b", ms_status);
|
||||
end
|
||||
|
||||
repeat (1000) @(posedge clk);
|
||||
$finish;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#100000000; // 100 ms hard timeout
|
||||
$display("[ERROR] Hard simulation timeout");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,181 @@
|
||||
`timescale 1ns/1ps
|
||||
`include "radar_params.vh"
|
||||
|
||||
// ============================================================================
|
||||
// tb_rxb_latency_measure.v
|
||||
//
|
||||
// Purpose: empirically measure the pipeline latency of
|
||||
// matched_filter_processing_chain — cycles between the first ADC sample in
|
||||
// and the first range_profile_valid out — for both the long-chirp path
|
||||
// (3000 samples padded to FFT_SIZE) and the short-chirp path (50 samples
|
||||
// padded to FFT_SIZE).
|
||||
//
|
||||
// The measured latency is the value LATENCY in latency_buffer should
|
||||
// compensate for so that ref_chirp_real/imag arrive at the chain in the
|
||||
// SAME cycle as the corresponding adc_data_i/q.
|
||||
//
|
||||
// Note: matched_filter_multi_segment buffers BUFFER_SIZE=2048 samples
|
||||
// before emitting to the chain regardless of how many active samples are in
|
||||
// the chirp (zero-pads short chirps). So both paths feed the chain
|
||||
// FFT_SIZE samples — the chain itself sees no chirp-type difference. This
|
||||
// test confirms whether a single LATENCY value works for both.
|
||||
// ============================================================================
|
||||
|
||||
module tb_rxb_latency_measure;
|
||||
|
||||
localparam CLK_PERIOD = 10.0; // 100 MHz
|
||||
localparam FFT_SIZE = `RP_FFT_SIZE; // 2048
|
||||
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
reg signed [15:0] adc_data_i;
|
||||
reg signed [15:0] adc_data_q;
|
||||
reg adc_valid;
|
||||
reg [5:0] chirp_counter;
|
||||
reg signed [15:0] ref_chirp_real;
|
||||
reg signed [15:0] ref_chirp_imag;
|
||||
wire signed [15:0] range_profile_i;
|
||||
wire signed [15:0] range_profile_q;
|
||||
wire range_profile_valid;
|
||||
wire [3:0] chain_state;
|
||||
|
||||
matched_filter_processing_chain dut (
|
||||
.clk (clk),
|
||||
.reset_n (reset_n),
|
||||
.adc_data_i (adc_data_i),
|
||||
.adc_data_q (adc_data_q),
|
||||
.adc_valid (adc_valid),
|
||||
.chirp_counter (chirp_counter),
|
||||
.ref_chirp_real (ref_chirp_real),
|
||||
.ref_chirp_imag (ref_chirp_imag),
|
||||
.range_profile_i (range_profile_i),
|
||||
.range_profile_q (range_profile_q),
|
||||
.range_profile_valid (range_profile_valid),
|
||||
.chain_state (chain_state)
|
||||
);
|
||||
|
||||
always #(CLK_PERIOD/2.0) clk = ~clk;
|
||||
|
||||
// Measurement state
|
||||
integer cycle_in_first; // cycle when first adc_valid pulse went HIGH
|
||||
integer cycle_out_first; // cycle when first range_profile_valid went HIGH
|
||||
integer cycle_count;
|
||||
reg saw_first_in;
|
||||
reg saw_first_out;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!reset_n) begin
|
||||
cycle_count <= 0;
|
||||
saw_first_in <= 0;
|
||||
saw_first_out <= 0;
|
||||
end else begin
|
||||
cycle_count <= cycle_count + 1;
|
||||
if (adc_valid && !saw_first_in) begin
|
||||
cycle_in_first <= cycle_count;
|
||||
saw_first_in <= 1;
|
||||
$display("[T=%0t] FIRST adc_valid=1 at cycle %0d", $time, cycle_count);
|
||||
end
|
||||
if (range_profile_valid && !saw_first_out) begin
|
||||
cycle_out_first <= cycle_count;
|
||||
saw_first_out <= 1;
|
||||
$display("[T=%0t] FIRST range_profile_valid=1 at cycle %0d", $time, cycle_count);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Stimulus
|
||||
integer k;
|
||||
integer pipeline_latency;
|
||||
|
||||
task feed_unit_chirp(input integer n_active_samples);
|
||||
// Feed FFT_SIZE samples: first n_active_samples are unit-impulse chirp
|
||||
// (1 at sample 0, 0 elsewhere) — represents a maximally simple input.
|
||||
// Both adc and ref get the same impulse for autocorrelation.
|
||||
integer j;
|
||||
begin
|
||||
for (j = 0; j < FFT_SIZE; j = j + 1) begin
|
||||
if (j == 0) begin
|
||||
adc_data_i <= 16'sd16384; // ~half full-scale
|
||||
adc_data_q <= 16'sd0;
|
||||
ref_chirp_real <= 16'sd16384;
|
||||
ref_chirp_imag <= 16'sd0;
|
||||
end else begin
|
||||
adc_data_i <= 16'sd0;
|
||||
adc_data_q <= 16'sd0;
|
||||
ref_chirp_real <= 16'sd0;
|
||||
ref_chirp_imag <= 16'sd0;
|
||||
end
|
||||
adc_valid <= 1'b1;
|
||||
@(posedge clk);
|
||||
end
|
||||
adc_valid <= 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
$dumpfile("tb_rxb_latency_measure.vcd");
|
||||
$dumpvars(0, tb_rxb_latency_measure);
|
||||
|
||||
clk = 0;
|
||||
reset_n = 0;
|
||||
adc_data_i = 0;
|
||||
adc_data_q = 0;
|
||||
adc_valid = 0;
|
||||
chirp_counter = 6'd0;
|
||||
ref_chirp_real = 0;
|
||||
ref_chirp_imag = 0;
|
||||
|
||||
repeat (4) @(posedge clk);
|
||||
reset_n = 1;
|
||||
repeat (4) @(posedge clk);
|
||||
|
||||
$display("\n=== RX-B latency measurement: chain pipeline depth ===");
|
||||
$display("FFT_SIZE = %0d", FFT_SIZE);
|
||||
$display("Feeding 2048-sample unit-impulse autocorrelation frame...");
|
||||
|
||||
// Two runs: short chirp (50 active) and long chirp (3000 active).
|
||||
// The chain itself is chirp-agnostic (always processes FFT_SIZE=2048
|
||||
// samples) — multi_segment upstream zero-pads — so both should give
|
||||
// identical chain latency. Confirms whether prior review's claim of
|
||||
// "different LATENCY for short chirp" is real or a misconception.
|
||||
feed_unit_chirp(50); // active samples; multi_segment zero-pads upstream
|
||||
|
||||
// Wait for output to start (poll every cycle, abort if too long)
|
||||
for (k = 0; k < 60000; k = k + 1) begin
|
||||
@(posedge clk);
|
||||
if (saw_first_out) k = 60001; // exit
|
||||
end
|
||||
|
||||
if (saw_first_out) begin
|
||||
pipeline_latency = cycle_out_first - cycle_in_first;
|
||||
$display("\n=== RESULT ===");
|
||||
$display("First adc_valid : cycle %0d", cycle_in_first);
|
||||
$display("First valid output : cycle %0d", cycle_out_first);
|
||||
$display("Pipeline latency : %0d cycles", pipeline_latency);
|
||||
$display("Current LATENCY in latency_buffer: 3187 cycles");
|
||||
$display("Delta (measured - configured): %0d cycles", pipeline_latency - 3187);
|
||||
$display("");
|
||||
$display("Interpretation:");
|
||||
$display(" - If delta is near 0, LATENCY=3187 is correct.");
|
||||
$display(" - Note: this measures only the chain's internal pipeline.");
|
||||
$display(" Full LATENCY also accounts for upstream multi_segment buffer fill.");
|
||||
end else begin
|
||||
$display("\n=== TIMEOUT ===");
|
||||
$display("range_profile_valid never asserted within 60000 cycles");
|
||||
$display("(behavioural FFT model in fft_engine.v may be much slower than");
|
||||
$display(" Xilinx FFT IP — try Vivado simulation for accurate timing)");
|
||||
end
|
||||
|
||||
// Wait a bit more to see if we get full 2048 outputs
|
||||
repeat (5000) @(posedge clk);
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Safety timeout
|
||||
initial begin
|
||||
#10000000; // 10 ms simulated time
|
||||
$display("[ERROR] Simulation timeout at 10 ms");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -88,9 +88,14 @@ module usb_data_interface_ft2232h (
|
||||
input wire cfar_valid,
|
||||
|
||||
// New inputs for bulk frame protocol (clk domain)
|
||||
input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in, // 9-bit range bin index
|
||||
input wire [4:0] doppler_bin_in, // 5-bit doppler bin index
|
||||
input wire frame_complete, // 1-cycle pulse from radar_receiver_final edge detector
|
||||
// [RX-D] Widened to RP_RANGE_BIN_WIDTH_MAX (9-bit on 50T, 12-bit on 200T)
|
||||
// to match upstream pipeline. In 3 km mode only bins 0..511 are exercised
|
||||
// and the frame wire protocol still emits 512×32=16384 cells. 20 km mode
|
||||
// (4096 bins, 131072 cells) requires a wire-protocol extension before
|
||||
// bins 512..4095 can be transported to the host.
|
||||
input wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] range_bin_in,
|
||||
input wire [4:0] doppler_bin_in, // 5-bit doppler bin index
|
||||
input wire frame_complete, // 1-cycle pulse from radar_receiver_final edge detector
|
||||
|
||||
// FT2232H Physical Interface (245 Synchronous FIFO mode)
|
||||
inout wire [7:0] ft_data, // 8-bit bidirectional data bus
|
||||
|
||||
Reference in New Issue
Block a user