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https://github.com/NawfalMotii79/PLFM_RADAR.git
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chore(mcu): C-14a — delete dead ADF4382A EZSync surface
Production firmware never used SYNC_METHOD_EZSYNC — both callsites
(main.cpp:938 recovery, main.cpp:1955 boot) pass SYNC_METHOD_TIMED.
The original audit C-14 flagged TX/RX SPI skew in EZSync's trigger
sequence, but the path was dead from production; only test_bug3
referenced it for spy-harness regression coverage.
Removed:
- SYNC_METHOD_EZSYNC enum value
- ADF4382A_SetupEZSync function (and declaration)
- ADF4382A_TriggerEZSync function (and declaration)
- EZSync branch in ADF4382A_Manager_Init (collapsed to unconditional
SetupTimedSync call)
- test_bug3_timed_sync_noop.c Test C (EZSync regression coverage)
Production header and test shim header both cleaned. SyncMethod enum
kept as single-value to avoid touching the 7 other test callers that
pass SYNC_METHOD_TIMED.
Residual concern (separate from original C-14): ADF4382A_TriggerTimedSync
uses the same TX-then-RX sw_sync SPI sequencing pattern as the deleted
EZSync trigger. ~5 µs SPI gap between TX-armed and RX-armed means TX
and RX may capture different SYNCP/SYNCN edges (60 MHz cycle = 16.7 ns,
~300 edges in the gap). External SYNCP only provides simultaneity if
both devices are armed before a common edge. Hardware bench-test
required to confirm operational tolerance; cannot fix in firmware
without DMA SPI burst rewrite.
Regression: 86/0 (matches baseline).
This commit is contained in:
@@ -64,7 +64,6 @@
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#define ADF4382A_MANAGER_ERROR_SPI -3
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typedef enum {
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SYNC_METHOD_EZSYNC = 0,
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SYNC_METHOD_TIMED = 1
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} SyncMethod;
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@@ -83,9 +82,7 @@ typedef struct {
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int ADF4382A_Manager_Init(ADF4382A_Manager *manager, SyncMethod method);
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int ADF4382A_Manager_Deinit(ADF4382A_Manager *manager);
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int ADF4382A_SetupTimedSync(ADF4382A_Manager *manager);
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int ADF4382A_SetupEZSync(ADF4382A_Manager *manager);
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int ADF4382A_TriggerTimedSync(ADF4382A_Manager *manager);
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int ADF4382A_TriggerEZSync(ADF4382A_Manager *manager);
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int ADF4382A_CheckLockStatus(ADF4382A_Manager *manager, bool *tx_locked, bool *rx_locked);
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int ADF4382A_SetOutputPower(ADF4382A_Manager *manager, uint8_t tx_power, uint8_t rx_power);
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int ADF4382A_EnableOutputs(ADF4382A_Manager *manager, bool tx_enable, bool rx_enable);
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@@ -5,15 +5,15 @@
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* messages but performed no hardware action.
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*
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* Fix: Implemented a sw_sync pulse (set true → 10us delay → set false) on
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* both TX and RX devices, mirroring EZSync's trigger pattern. With
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* timed_sync_setup already programmed, the devices synchronize their output
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* dividers to the SYNCP/SYNCN clock edge when sw_sync is asserted.
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* both TX and RX devices. With timed_sync_setup already programmed, the
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* devices synchronize their output dividers to the SYNCP/SYNCN clock edge
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* when sw_sync is asserted.
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*
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* Test strategy (post-fix):
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* 1. Initialize manager with SYNC_METHOD_TIMED.
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* 2. Reset spy log, call TriggerTimedSync().
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* 3. Verify 4 SPY_ADF4382_SET_SW_SYNC records (TX set, RX set, TX clear,
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* RX clear) — same count as EZSync.
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* RX clear).
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* 4. Verify the set/clear ordering is correct.
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******************************************************************************/
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#include "adf4382a_manager.h"
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@@ -83,19 +83,7 @@ int main(void)
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assert(sw_idx == 4);
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printf(" PASS: Ordering is correct (set TX, set RX, clear TX, clear RX)\n");
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/* ---- Test C: Compare with EZSync — both should produce 4 sw_sync calls ---- */
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mgr.sync_method = SYNC_METHOD_EZSYNC;
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spy_reset();
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ret = ADF4382A_TriggerEZSync(&mgr);
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assert(ret == ADF4382A_MANAGER_OK);
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int ezsync_count = spy_count_type(SPY_ADF4382_SET_SW_SYNC);
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printf("\n EZSync sw_sync count: %d (expected 4, same as timed sync)\n",
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ezsync_count);
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assert(ezsync_count == 4);
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printf(" PASS: Both sync methods now issue the same hw trigger pattern\n");
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/* Cleanup */
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mgr.sync_method = SYNC_METHOD_TIMED;
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ADF4382A_Manager_Deinit(&mgr);
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printf("\n=== Bug #3: ALL TESTS PASSED (post-fix) ===\n\n");
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