chore(mcu): C-14a — delete dead ADF4382A EZSync surface

Production firmware never used SYNC_METHOD_EZSYNC — both callsites
(main.cpp:938 recovery, main.cpp:1955 boot) pass SYNC_METHOD_TIMED.
The original audit C-14 flagged TX/RX SPI skew in EZSync's trigger
sequence, but the path was dead from production; only test_bug3
referenced it for spy-harness regression coverage.

Removed:
  - SYNC_METHOD_EZSYNC enum value
  - ADF4382A_SetupEZSync function (and declaration)
  - ADF4382A_TriggerEZSync function (and declaration)
  - EZSync branch in ADF4382A_Manager_Init (collapsed to unconditional
    SetupTimedSync call)
  - test_bug3_timed_sync_noop.c Test C (EZSync regression coverage)

Production header and test shim header both cleaned. SyncMethod enum
kept as single-value to avoid touching the 7 other test callers that
pass SYNC_METHOD_TIMED.

Residual concern (separate from original C-14): ADF4382A_TriggerTimedSync
uses the same TX-then-RX sw_sync SPI sequencing pattern as the deleted
EZSync trigger. ~5 µs SPI gap between TX-armed and RX-armed means TX
and RX may capture different SYNCP/SYNCN edges (60 MHz cycle = 16.7 ns,
~300 edges in the gap). External SYNCP only provides simultaneity if
both devices are armed before a common edge. Hardware bench-test
required to confirm operational tolerance; cannot fix in firmware
without DMA SPI burst rewrite.

Regression: 86/0 (matches baseline).
This commit is contained in:
Jason
2026-05-04 21:05:50 +05:45
parent 38ee73a05c
commit 53f7d1e3ee
4 changed files with 17 additions and 137 deletions
@@ -64,7 +64,6 @@
#define ADF4382A_MANAGER_ERROR_SPI -3
typedef enum {
SYNC_METHOD_EZSYNC = 0,
SYNC_METHOD_TIMED = 1
} SyncMethod;
@@ -83,9 +82,7 @@ typedef struct {
int ADF4382A_Manager_Init(ADF4382A_Manager *manager, SyncMethod method);
int ADF4382A_Manager_Deinit(ADF4382A_Manager *manager);
int ADF4382A_SetupTimedSync(ADF4382A_Manager *manager);
int ADF4382A_SetupEZSync(ADF4382A_Manager *manager);
int ADF4382A_TriggerTimedSync(ADF4382A_Manager *manager);
int ADF4382A_TriggerEZSync(ADF4382A_Manager *manager);
int ADF4382A_CheckLockStatus(ADF4382A_Manager *manager, bool *tx_locked, bool *rx_locked);
int ADF4382A_SetOutputPower(ADF4382A_Manager *manager, uint8_t tx_power, uint8_t rx_power);
int ADF4382A_EnableOutputs(ADF4382A_Manager *manager, bool tx_enable, bool rx_enable);
@@ -5,15 +5,15 @@
* messages but performed no hardware action.
*
* Fix: Implemented a sw_sync pulse (set true 10us delay set false) on
* both TX and RX devices, mirroring EZSync's trigger pattern. With
* timed_sync_setup already programmed, the devices synchronize their output
* dividers to the SYNCP/SYNCN clock edge when sw_sync is asserted.
* both TX and RX devices. With timed_sync_setup already programmed, the
* devices synchronize their output dividers to the SYNCP/SYNCN clock edge
* when sw_sync is asserted.
*
* Test strategy (post-fix):
* 1. Initialize manager with SYNC_METHOD_TIMED.
* 2. Reset spy log, call TriggerTimedSync().
* 3. Verify 4 SPY_ADF4382_SET_SW_SYNC records (TX set, RX set, TX clear,
* RX clear) same count as EZSync.
* RX clear).
* 4. Verify the set/clear ordering is correct.
******************************************************************************/
#include "adf4382a_manager.h"
@@ -83,19 +83,7 @@ int main(void)
assert(sw_idx == 4);
printf(" PASS: Ordering is correct (set TX, set RX, clear TX, clear RX)\n");
/* ---- Test C: Compare with EZSync — both should produce 4 sw_sync calls ---- */
mgr.sync_method = SYNC_METHOD_EZSYNC;
spy_reset();
ret = ADF4382A_TriggerEZSync(&mgr);
assert(ret == ADF4382A_MANAGER_OK);
int ezsync_count = spy_count_type(SPY_ADF4382_SET_SW_SYNC);
printf("\n EZSync sw_sync count: %d (expected 4, same as timed sync)\n",
ezsync_count);
assert(ezsync_count == 4);
printf(" PASS: Both sync methods now issue the same hw trigger pattern\n");
/* Cleanup */
mgr.sync_method = SYNC_METHOD_TIMED;
ADF4382A_Manager_Deinit(&mgr);
printf("\n=== Bug #3: ALL TESTS PASSED (post-fix) ===\n\n");