fix(ci): restore develop CI green — ruff T20 exemption + ADAR1000 setter regex extension

Two independent root causes landed together in the recent develop merge
burst, leaving CI red on every commit since. Both fixes are narrow parser/
config updates; no code logic changes.

1. Ruff T201 violation in 8_Utils/Python/LUT.py:24

   The recent restoration of `print(f"8'd{val},")` (replacing `pass`) made
   the LUT generator functional again, but the file is not in pyproject's
   per-file-ignores so ruff's T20 rule flags it. Add a narrow per-file-
   ignore for T20 specifically scoped to LUT.py.

2. Five tests in TestTier1Adar1000ChannelRegisterRoundTrip

   The recent SPI/ADC error-propagation refactor on ADAR1000_Manager.cpp
   changed the four setters adarSet{Rx,Tx}{Phase,VgaGain} from `void` to
   `bool` returns AND introduced the `ok = setter(args) && ok` error-chain
   idiom at internal call sites. The test class's parser regexes were
   authored for the pre-refactor convention.

   Two regex extensions:

     * Body parser: `void\s+...` -> `(?:void|bool)\s+...` so bodies are
       found under either return-type convention.
     * Caller finder: `\)\s*;` -> `\)(?:\s*&&\s*\w+)*\s*;` so the
       error-chain idiom is matched alongside standalone calls.

   Body extraction logic, REG_CHn_XXX + <expr> regex, symbolic AST
   evaluation, round-trip strict-equality, and stride detection are all
   unchanged. The two regex extensions only acknowledge the new C++
   conventions introduced by the SPI/ADC refactor.

Verified locally:
- `uv run ruff check .` returns 0 errors.
- `uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py`
  passes 51 tests + 5 skipped (Tier2VerilogCosim local-only, requires
  iverilog which is installed in CI).
- `uv run pytest 9_Firmware/9_3_GUI/test_v7.py` passes 83 tests + 3
  skipped (no regression).

pyproject.toml

@@ -49,3 +49,6 @@ select = [
 "test_*.py" = ["ARG", "T20", "ERA"]
 # Re-export modules: unused imports are intentional
 "v7/hardware.py" = ["F401"]
+# 8_Utils/Python/LUT.py is a single-purpose Verilog LUT generator whose only
+# output is `print(f"8'd{val},")` per the file's docstring intent.
+"8_Utils/Python/LUT.py" = ["T20"]