fix(ci): restore develop CI green — ruff T20 exemption + ADAR1000 setter regex extension

Two independent root causes landed together in the recent develop merge
burst, leaving CI red on every commit since. Both fixes are narrow parser/
config updates; no code logic changes.

1. Ruff T201 violation in 8_Utils/Python/LUT.py:24

   The recent restoration of `print(f"8'd{val},")` (replacing `pass`) made
   the LUT generator functional again, but the file is not in pyproject's
   per-file-ignores so ruff's T20 rule flags it. Add a narrow per-file-
   ignore for T20 specifically scoped to LUT.py.

2. Five tests in TestTier1Adar1000ChannelRegisterRoundTrip

   The recent SPI/ADC error-propagation refactor on ADAR1000_Manager.cpp
   changed the four setters adarSet{Rx,Tx}{Phase,VgaGain} from `void` to
   `bool` returns AND introduced the `ok = setter(args) && ok` error-chain
   idiom at internal call sites. The test class's parser regexes were
   authored for the pre-refactor convention.

   Two regex extensions:

     * Body parser: `void\s+...` -> `(?:void|bool)\s+...` so bodies are
       found under either return-type convention.
     * Caller finder: `\)\s*;` -> `\)(?:\s*&&\s*\w+)*\s*;` so the
       error-chain idiom is matched alongside standalone calls.

   Body extraction logic, REG_CHn_XXX + <expr> regex, symbolic AST
   evaluation, round-trip strict-equality, and stride detection are all
   unchanged. The two regex extensions only acknowledge the new C++
   conventions introduced by the SPI/ADC refactor.

Verified locally:
- `uv run ruff check .` returns 0 errors.
- `uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py`
  passes 51 tests + 5 skipped (Tier2VerilogCosim local-only, requires
  iverilog which is installed in CI).
- `uv run pytest 9_Firmware/9_3_GUI/test_v7.py` passes 83 tests + 3
  skipped (no regression).

9_Firmware/tests/cross_layer/test_cross_layer_contract.py

@@ -768,14 +768,21 @@ def _safe_eval_int_expr(expr, **variables):
 
 def _extract_adar_helper_sites(manager_cpp, setter_names):
     """
-    For each setter, locate the body of ``void ADAR1000Manager::<setter>``
-    and return a list of (setter, base_register, offset_expr_c, stride)
-    for every ``REG_CHn_XXX + <expr>`` memory-address assignment.
+    For each setter, locate the body of ``void`` or ``bool``
+    ``ADAR1000Manager::<setter>`` and return a list of (setter,
+    base_register, offset_expr_c, stride) for every ``REG_CHn_XXX +
+    <expr>`` memory-address assignment.
+
+    The setters originally returned ``void``. After the SPI/ADC error-
+    propagation refactor they return ``bool`` so callers can observe
+    write/read failures. The body form (``REG_CHn_XXX + <expr>``,
+    ``(channel - 1) & 0x03`` mask, ``* 2`` stride for phase I/Q) is
+    unchanged.
     """
     sites = []
     for setter in setter_names:
         m = re.search(
-            rf"void\s+ADAR1000Manager::{setter}\s*\([^)]*\)\s*\{{(.+?)^\}}",
+            rf"(?:void|bool)\s+ADAR1000Manager::{setter}\s*\([^)]*\)\s*\{{(.+?)^\}}",
             manager_cpp,
             re.MULTILINE | re.DOTALL,
         )
@@ -818,9 +825,15 @@ def _extract_adar_caller_sites(sources, setter):
     call sites fit on one line; a future multi-line refactor would drop
     callers from the scan, which the round-trip test surfaces loudly via
     `assert callers` (rather than silently missing a site).
+
+    Two terminating forms are accepted:
+      * ``setter(args);``                                — standalone call.
+      * ``ok = setter(args) && ok;`` (one or more chains) — error-propagation
+        idiom introduced by the SPI/ADC refactor where setters return
+        ``bool`` and callers AND the result into a running success flag.
     """
     out = []
-    call_re = re.compile(rf"\b{setter}\s*\(([^;]*?)\)\s*;")
+    call_re = re.compile(rf"\b{setter}\s*\(([^;]*?)\)(?:\s*&&\s*\w+)*\s*;")
     for filename, text in sources:
         for line_no, line in enumerate(text.splitlines(), start=1):
             # Skip method definition / declaration lines.

pyproject.toml

@@ -49,3 +49,6 @@ select = [
 "test_*.py" = ["ARG", "T20", "ERA"]
 # Re-export modules: unused imports are intentional
 "v7/hardware.py" = ["F401"]
+# 8_Utils/Python/LUT.py is a single-purpose Verilog LUT generator whose only
+# output is `print(f"8'd{val},")` per the file's docstring intent.
+"8_Utils/Python/LUT.py" = ["T20"]