Jason f39a78cb1e chore(fpga): untrack TB-generated CSV, ignore a.out ...

rx_final_doppler_out.csv is written by tb_radar_receiver_final.v on
every run via $fopen — it is a test-run artifact, not an oracle. It
was mistakenly tracked in an earlier commit, causing unnecessary
churn on every sim. Remove from the index and ignore going forward.

Also ignore stray a.out from iverilog one-shot compiles.

Golden references (.hex, .mem, doppler_golden_py_*.csv) remain
tracked — they are load-bearing oracles used by MF / Doppler /
receiver cosim testbenches.

2026-04-22 13:36:03 +05:45

..

9_1_Microcontroller

refactor(mcu): remove redundant ADAR1000 T/R SPI paths (FPGA-owned)

2026-04-21 01:09:38 +05:45

9_2_FPGA

chore(fpga): untrack TB-generated CSV, ignore a.out

2026-04-22 13:36:03 +05:45

9_3_GUI

fix(gui): align radar parameters to FPGA truth (radar_scene.py)

2026-04-16 21:35:01 +05:45

tests/cross_layer

test(fpga): F-3.2 add DDC cosim fuzz runner with seed sweep

2026-04-20 15:48:34 +05:45

tools

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