Jason e8eb24f4f5 style(fpga): drop dead regex in gen_chirp_mem parser ...

Leftover from two alternative parsing approaches; the unused pat
triggered ruff F841. Only line_pat is actually used.

2026-04-23 04:48:23 +05:45

..

real_data

…

adc_dc.hex

…

adc_multi_target.hex

…

adc_noise_only.hex

…

adc_sine_1mhz.hex

…

adc_single_target.hex

…

bb_mf_test_i.hex

…

bb_mf_test_q.hex

…

compare_dc.csv

…

compare_doppler.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

compare_mf_chirp.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

compare_mf_dc.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

compare_mf_impulse.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

compare_mf_tone5.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

compare_mf.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

compare_multi_target.csv

…

compare_noise_only.csv

…

compare_sine_1mhz.csv

…

compare_single_target.csv

…

compare.py

…

doppler_golden_py_moving.csv

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

doppler_golden_py_moving.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

doppler_golden_py_stationary.csv

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

doppler_golden_py_stationary.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

doppler_golden_py_two_targets.csv

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

doppler_golden_py_two_targets.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

doppler_input_moving.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

doppler_input_stationary.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

doppler_input_two_targets.hex

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

fpga_model.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

gen_chirp_mem.py

style(fpga): drop dead regex in gen_chirp_mem parser

2026-04-23 04:48:23 +05:45

gen_doppler_golden.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

gen_mf_cosim_golden.py

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

gen_multiseg_golden.py

…

mf_golden_py_chirp.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_dc.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_i_chirp.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_i_dc.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_i_impulse.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_i_tone5.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_impulse.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_q_chirp.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_q_dc.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_q_impulse.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_q_tone5.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_golden_py_tone5.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_chirp_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_chirp_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_dc_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_dc_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_impulse_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_impulse_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_tone5_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_ref_tone5_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_chirp_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_chirp_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_dc_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_dc_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_impulse_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_impulse_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_tone5_i.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

mf_sig_tone5_q.hex

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

multiseg_golden_seg0_i.hex

…

multiseg_golden_seg0_q.hex

…

multiseg_golden_seg1_i.hex

…

multiseg_golden_seg1_q.hex

…

multiseg_golden_seg2_i.hex

…

multiseg_golden_seg2_q.hex

…

multiseg_golden_seg3_i.hex

…

multiseg_golden_seg3_q.hex

…

multiseg_golden.csv

…

multiseg_input_i.hex

…

multiseg_input_q.hex

…

multiseg_ref_seg0_i.hex

…

multiseg_ref_seg0_q.hex

…

multiseg_ref_seg1_i.hex

…

multiseg_ref_seg1_q.hex

…

multiseg_ref_seg2_i.hex

…

multiseg_ref_seg2_q.hex

…

multiseg_ref_seg3_i.hex

…

multiseg_ref_seg3_q.hex

…

multiseg_short_golden_i.hex

…

multiseg_short_golden_q.hex

…

multiseg_short_golden.csv

…

multiseg_short_input_i.hex

…

multiseg_short_input_q.hex

…

multiseg_short_ref_i.hex

…

multiseg_short_ref_q.hex

…

radar_scene.py

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

ref_chirp_i.hex

…

ref_chirp_q.hex

…

rtl_bb_dc.csv

…

rtl_bb_multi_target.csv

…

rtl_bb_noise_only.csv

…

rtl_bb_sine_1mhz.csv

…

rtl_bb_single_target.csv

…

rtl_mf_chirp.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

rtl_mf_dc.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

rtl_mf_impulse.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

rtl_mf_tone5.csv

merge(wave3/tier2): port testbenches and cosim goldens for fft-2048

2026-04-21 03:04:52 +05:45

scenario_info.txt

…

validate_mem_files.py

…