Jason e506a80db5 Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

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Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

ad9484_interface_400m.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cdc_modules.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

chirp_lut_init.v

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chirp_memory_loader_param.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cic_decimator_4x_enhanced.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

cntrt.xdc

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

dac_interface_single.v

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ddc_400m.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

ddc_input_interface.v

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doppler_processor.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

edge_detector.v

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fft_1024_forward.v

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fft_1024_inverse.v

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fft_engine.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

fft_twiddle_32.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fft_twiddle_1024.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fir_lowpass.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

frequency_matched_filter.v

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latency_buffer_2159.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

level_shifter_interface.v

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long_chirp_seg0_i.mem

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long_chirp_seg0_q.mem

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long_chirp_seg1_i.mem

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long_chirp_seg1_q.mem

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long_chirp_seg2_i.mem

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long_chirp_seg2_q.mem

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long_chirp_seg3_i.mem

Add missing long_chirp_seg3 memory files for complete chirp waveform

2026-03-15 18:06:35 +02:00

long_chirp_seg3_q.mem

Add missing long_chirp_seg3 memory files for complete chirp waveform

2026-03-15 18:06:35 +02:00

lvds_to_cmos_400m.v

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matched_filter_multi_segment.v

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matched_filter_processing_chain.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

nco_400m_enhanced.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

plfm_chirp_controller.v

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radar_mode_controller.v

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radar_receiver_final.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

radar_system_tb.v

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radar_system_top.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

radar_transmitter.v

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range_bin_decimator.v

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short_chirp_i.mem

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short_chirp_q.mem

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usb_data_interface.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

usb_packet_analyzer.v

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xfft_32.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00