Jason d6462c6d5b docs(fpga): PR-X.2 F-7.2 — refresh adc_clk_mmcm.xdc comments to SDR IFF ...

Constraint values are unchanged — only the explanatory comments are
refreshed to match the post-AUDIT-C4 (2026-05-01) RTL.

  - "IDDR outputs"          → "IFF Q output"
  - "adc_data_{rise,fall}_bufg" → "adc_data_iff_bufg"
  - "the IDDR ~1.4ns before the clock" → "the IOB-packed IFF ~1.4ns
    before the clock"
  - hold-waiver header "BUFIO-clocked IDDR" → "BUFIO-clocked IFF, SDR"
  - "BUFIO/IDDR domain"     → "BUFIO/IFF domain"

The 3.000 ns set_max_delay (BUFIO ↔ clk_mmcm_out0), the
set_false_path -hold on adc_d_p[*]/adc_or_p, the LOCKED-pin
through-waiver, and the 0.150 ns set_clock_uncertainty all remain
bit-identical — the IFF capture has the exact same source-synchronous
timing argument as the prior IDDR did.

One reference to "IDDR" deliberately kept inside a negation
("no IDDR, no rise/fall demux") — explicitly contrasts the current
SDR topology with the broken pre-C-4 shape so a reader who finds the
old vocabulary in git history understands what changed.

2026-05-05 13:46:12 +05:45

..

9_1_Microcontroller

refactor(mcu): PR-W F-6.7 — privatize setADTR1107Mode

2026-05-05 11:30:46 +05:45

9_2_FPGA

docs(fpga): PR-X.2 F-7.2 — refresh adc_clk_mmcm.xdc comments to SDR IFF

2026-05-05 13:46:12 +05:45

9_3_GUI

test(v7): port live-vs-replay physical-units parity guard from develop

2026-05-05 09:30:26 +05:45

tests/cross_layer

chore(tests): retire v1 cross-layer iverilog cosim tier

2026-05-04 21:06:34 +05:45

tools

…