Jason bec578a5e7 Revert "fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin)" ...

This reverts commit 30279e8c4d.

2026-04-20 21:47:19 +05:45

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constraints

Revert "fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin)"

2026-04-20 21:47:19 +05:45

formal

fix(rtl,gui,cosim,formal): adapt surrounding files for dual 16-pt FFT (follow-up to PR #33)

2026-04-06 23:15:50 +03:00

scripts

Revert "fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin)"

2026-04-20 21:47:19 +05:45

tb

test(fpga): F-3.2 add DDC cosim fuzz runner with seed sweep

2026-04-20 15:48:34 +05:45

.gitignore

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ad9484_interface_400m.v

fix(fpga): F-0.1 wire AD9484 OR overrange pin into diagnostics

2026-04-20 15:48:34 +05:45

adc_clk_mmcm_integration.md

Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix

2026-03-19 22:59:46 +02:00

adc_clk_mmcm.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

cdc_modules.v

fix(pre-bringup): second-batch P1/P2/P3 audit findings

2026-04-20 14:28:22 +05:45

cfar_ca.v

Pipeline CFAR noise computation: break critical path for timing closure

2026-03-20 05:24:08 +02:00

chirp_memory_loader_param.v

E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)

2026-03-20 01:45:00 +02:00

cic_decimator_4x_enhanced.v

fix(fpga): audit F-2026-04-20-A/B — CIC reset fan-out + BUFIO→BUFG max_delay

2026-04-20 20:20:43 +05:45

dac_interface_single.v

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ddc_400m.v

fix(pre-bringup): second-batch P1/P2/P3 audit findings

2026-04-20 14:28:22 +05:45

ddc_input_interface.v

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doppler_processor.v

Fix staggered-PRF Doppler processing with dual 16-point FFTs

2026-03-27 23:05:28 +02:00

edge_detector.v

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fft_engine.v

FFT engine: merge SHIFT into WRITE (5→4 cycle butterfly, 20% throughput) + barrel-shift twiddle index

2026-03-20 00:20:59 +02:00

fft_twiddle_16.mem

Fix staggered-PRF Doppler processing with dual 16-point FFTs

2026-03-27 23:05:28 +02:00

fft_twiddle_1024.mem

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fir_lowpass.v

fix(rtl): force FIR adder tree to fabric to free 30 DSPs for FFT butterfly on 50T

2026-04-07 14:45:47 +03:00

fpga_self_test.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

frequency_matched_filter.v

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latency_buffer.v

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long_chirp_lut.mem

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long_chirp_seg0_i.mem

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long_chirp_seg0_q.mem

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long_chirp_seg1_i.mem

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long_chirp_seg1_q.mem

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long_chirp_seg2_i.mem

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long_chirp_seg2_q.mem

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long_chirp_seg3_i.mem

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long_chirp_seg3_q.mem

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matched_filter_multi_segment.v

Fix matched filter synth errors: overlap_copy_count part-select width, add FSM default

2026-03-19 20:53:29 +02:00

matched_filter_processing_chain.v

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mti_canceller.v

fix(pre-bringup): resolve P0 + quick-win P1 findings from 2026-04-19 audit

2026-04-20 13:48:36 +05:45

nco_400m_enhanced.v

fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H

2026-04-18 20:34:52 +05:45

plfm_chirp_controller.v

E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)

2026-03-20 01:45:00 +02:00

radar_mode_controller.v

Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)

2026-03-19 23:54:48 +02:00

radar_receiver_final.v

fix(fpga): F-0.1 wire AD9484 OR overrange pin into diagnostics

2026-04-20 15:48:34 +05:45

radar_system_top_50t.v

Revert "fix(fpga): move IBUF+BUFIO+BUFR into 50T wrapper (same scope as pad)"

2026-04-20 21:47:19 +05:45

radar_system_top_te0712_dev.v

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radar_system_top_te0713_dev.v

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radar_system_top_te0713_umft601x_dev.v

feat(fpga): make FT2232H default USB interface, rewrite FT601 write FSM, add clock-loss watchdog

2026-04-16 16:18:52 +05:45

radar_system_top.v

Revert "fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin)"

2026-04-20 21:47:19 +05:45

radar_transmitter.v

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range_bin_decimator.v

Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)

2026-03-20 04:38:35 +02:00

run_regression.sh

fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H

2026-04-18 20:34:52 +05:45

rx_gain_control.v

fix: 9 bugs from code review — RTL sign-ext & snapshot, thread safety, protocol fixes

2026-04-13 23:35:10 +05:45

short_chirp_i.mem

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short_chirp_q.mem

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usb_data_interface_ft2232h.v

feat(fpga): make FT2232H default USB interface, rewrite FT601 write FSM, add clock-loss watchdog

2026-04-16 16:18:52 +05:45

usb_data_interface.v

fix: clarify comments — AGC width, dual-USB docstring, BE datasheet ref

2026-04-16 17:51:09 +05:45

xfft_16.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00