Jason 8f51646a2e test(fpga): xsim runner for tb_matched_filter_processing_chain ...

Compiles + runs the MF chain TB under Vivado XSim with FFT_USE_XILINX_IP
defined, exercising matched_filter_processing_chain →
fft_engine_axi_bridge → xfft_2048 → real LogiCORE FFT v9.1 IP.
Symlinks tb/ into the work dir so $readmemh("tb/mf_golden_*.hex")
resolves from xsim's CWD.

This validates the chain glue (FSM, BRAMs, conj-mult, sat-truncate) works
correctly against the actual IP timing/scaling, not just the iverilog
fft_engine.v fallback.

Output: /tmp/mf_chain_xsim.log; xsim run takes ~40 min on the remote box.

2026-05-02 11:16:17 +05:45

..

50t

test(fpga): xsim runner for tb_matched_filter_processing_chain

2026-05-02 11:16:17 +05:45

200t

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

te0712

fix(xdc): add hold false_path for ADC IDDR + reorganize build scripts by target

2026-04-07 15:13:13 +03:00

te0713

fix(xdc): add hold false_path for ADC IDDR + reorganize build scripts by target

2026-04-07 15:13:13 +03:00

utils

fix(xdc): add hold false_path for ADC IDDR + reorganize build scripts by target

2026-04-07 15:13:13 +03:00