NawfalMotii79-PLFM_RADAR

constraints

feat(fpga,mcu,gui): PR-AB.b — drift-free dwell sync via DIG_6 frame_pulse + AGC always-on policy

2026-05-07 13:29:48 +05:45

formal

fix(fpga): PR-Y.1 + PR-X.3 — DC notch boundary, audit cleanups, formal retarget

2026-05-06 01:23:21 +05:45

ip/xfft_2048_ip

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45

scripts

fix(fpga): PR-X.1.b — close F-7.4 on real Vivado xsim

2026-05-05 13:33:48 +05:45

tb

test(fpga): C-3 — align DDC ADC format test with exact conversion

2026-05-09 14:07:54 +05:45

.gitignore

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

ad9484_interface_400m.v

fix(fpga): PR-X.1.b — close F-7.4 on real Vivado xsim

2026-05-05 13:33:48 +05:45

adc_clk_mmcm.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

cdc_async_fifo.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

cdc_modules.v

fix(pre-bringup): second-batch P1/P2/P3 audit findings

2026-04-20 14:28:22 +05:45

cfar_ca.v

docs(cfar): PR-M.4 — note Doppler-window dependency on CFAR alpha

2026-05-01 18:53:24 +05:45

chirp_reference_rom.v

chirp-v2 PR-C: chirp_reference_rom replaces chirp_memory_loader_param

2026-04-30 19:37:43 +05:45

chirp_scheduler.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

cic_decimator_4x_enhanced.v

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

dac_interface_single.v

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ddc_400m.v

fix(fpga): PR-X.1 F-7.6 — correct offset-binary mid-scale conversion in DDC

2026-05-05 12:12:04 +05:45

ddc_input_interface.v

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doppler_processor.v

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

edge_detector.v

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fft_engine_axi_bridge.v

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45

fft_engine.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

fft_twiddle_16.mem

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fft_twiddle_1024.mem

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fft_twiddle_2048.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fir_lowpass.v

AUDIT-S17: document fir_lowpass +4.96 dB DC gain and CIC-droop comp

2026-04-30 10:08:34 +05:45

fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

frequency_matched_filter.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

matched_filter_multi_segment.v

fix(rx): PR-J.2 — pre-collect chirp + slide segments (LONG hang)

2026-05-01 15:07:19 +05:45

matched_filter_processing_chain.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

mti_canceller.v

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

nco_400m_enhanced.v

fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H

2026-04-18 20:34:52 +05:45

plfm_chirp_controller_v2.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

radar_params.vh

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

radar_receiver_final.v

fix(fpga): PR-Y.1 + PR-X.3 — DC notch boundary, audit cleanups, formal retarget

2026-05-06 01:23:21 +05:45

radar_system_top_50t.v

feat(fpga,mcu,gui): PR-AB.b — drift-free dwell sync via DIG_6 frame_pulse + AGC always-on policy

2026-05-07 13:29:48 +05:45

radar_system_top_te0712_dev.v

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radar_system_top_te0713_dev.v

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radar_system_top_te0713_umft601x_dev.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_system_top.v

feat(fpga,gui): PR-AC.1 — M-5 status pkt 30→34 B for medium_chirp/medium_listen readback

2026-05-07 15:20:09 +05:45

radar_transmitter.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

range_bin_decimator.v

AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator

2026-04-30 09:04:01 +05:45

run_regression.sh

feat(fpga,mcu,gui): PR-AB.b — drift-free dwell sync via DIG_6 frame_pulse + AGC always-on policy

2026-05-07 13:29:48 +05:45

rx_gain_control.v

fix(fpga): PR-Y.1 + PR-X.3 — DC notch boundary, audit cleanups, formal retarget

2026-05-06 01:23:21 +05:45

rx_long_seg0_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg0_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg1_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg1_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_medium_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_medium_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_short_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_short_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_long_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_medium_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_short_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

usb_data_interface_ft2232h.v

feat(fpga,gui): PR-AC.1 — M-5 status pkt 30→34 B for medium_chirp/medium_listen readback

2026-05-07 15:20:09 +05:45

usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

xfft_16.v

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xfft_2048.v

fix(fpga): PR-O.8.1 — drop stale BFP-era ports, fix xsim include path

2026-05-02 10:20:10 +05:45