Jason ae61cf5dc5 test(fpga): wire 4 orphan TBs; add nightly DDC fuzz CI job ...

Regression coverage additions in run_regression.sh:
  - Phase 2: tb_ddc_400m (standalone DDC unit, 7 checks)
  - Phase 3: tb_freq_matched_filter (14 checks)
  - Phase 4: tb_ddc_input_interface (26 checks), tb_latency_buffer
    (13 checks)

All four existed in tb/ but had no regression runner entry; now gate
every push/PR. Deletes tb/tb_multiseg_cosim.v — stale against the
current RP_FFT_SIZE=2048 / RP_LONG_SEGMENTS_3KM=2 (TB hardcoded 1024/4,
15/32 checks fail on current RTL). Re-add when the multi-segment TB
is reworked for the 2048-point pipeline.

CI: new fpga-fuzz job running test_ddc_cosim_fuzz.py -m slow
(100-seed sweep). Gated to schedule (07:00 UTC daily) +
workflow_dispatch so PRs stay fast.

2026-04-23 06:31:26 +05:45

..

ci-tests.yml

test(fpga): wire 4 orphan TBs; add nightly DDC fuzz CI job

2026-04-23 06:31:26 +05:45