mirror of
https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-09 15:07:14 +00:00
Jason
977434a5f6
The header had two claims that "valid samples arrive every ~4 cycles" at the FIR boundary. That is false in the production wiring: the CIC `_4x` decimator turns clk_400m into a 100 M-pulse-per-second stream, then cdc_adc_to_processing crosses that into clk_100m where dst_valid asserts every cycle in steady state. The 4:1 ratio applies between the two clock domains, not as further sub-sampling inside clk_100m. This matters because the 32-tap coefficients were designed for the 25 MSPS rate the wrong comment described, but the FIR is actually being driven at 100 MSPS. The cutoff sits 4x higher than intended; existing tests pass because the 36-bit accumulator silently wraps on large sustained inputs (see RX-NEW-3 in the project ledger). Comment-only commit. No RTL behaviour change. Any future DSP-saving rework — symmetric pre-adder, 4:1 fold, Xilinx FIR Compiler — needs a designer call on whether to redesign coefficients for 100 MSPS, add a real decimation stage to hit 25 MSPS, or keep the current accidental behaviour.
329 lines
14 KiB
Verilog
329 lines
14 KiB
Verilog
`timescale 1ns / 1ps
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module fir_lowpass_parallel_enhanced (
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input wire clk,
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input wire reset_n,
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input wire signed [17:0] data_in,
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input wire data_valid,
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output reg signed [17:0] data_out,
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output reg data_out_valid,
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output wire fir_ready,
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output wire filter_overflow
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);
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parameter TAPS = 32;
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parameter COEFF_WIDTH = 18;
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parameter DATA_WIDTH = 18;
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parameter ACCUM_WIDTH = 36;
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// ============================================================================
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// Pipelined FIR filter for 100 MHz timing closure
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//
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// Problem: The original fully-combinatorial adder tree for 32 multiply products
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// created a 31-deep DSP48E1 PCOUT cascade chain taking 56.6ns (WNS = -48.325ns).
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//
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// Solution: 5-stage pipelined binary adder tree with registered outputs at
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// each level, plus BREG (coefficient register) and MREG (multiply output
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// register) stages for DSP48E1 absorption. Each stage performs at most one
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// pairwise addition (~1.7ns DSP hop), easily fitting in the 10ns clock period.
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//
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// Pipeline stages:
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// Cycle 0: data_valid → shift delay line + latch coefficients (BREG)
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// Cycle 1: Combinatorial multiply latched into mult_reg (MREG)
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// Cycle 2: 16 pairwise sums of 32 multiply results (level 0)
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// Cycle 3: 8 pairwise sums (level 1)
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// Cycle 4: 4 pairwise sums (level 2)
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// Cycle 5: 2 pairwise sums (level 3)
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// Cycle 6: 1 final sum → accumulator_reg (level 4)
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// Cycle 7: Output saturation/rounding
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//
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// Total latency: 9 cycles from data_valid to data_out_valid
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// (was 7 before BREG+MREG addition — +2 cycles for DSP48 pipelining)
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// Throughput: 1 sample per cycle (fully pipelined)
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//
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// Input rate: 100 MSPS at clk_100m (data_valid asserted EVERY cycle in
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// steady state). The CIC `_4x` decimator drops 4:1 from clk_400m → 100 M
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// pulses/s, then the cdc_adc_to_processing CDC into clk_100m emits one
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// dst_valid per dst_clk cycle (Gray-toggle handshake at matching rate).
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// A previous comment here claimed "samples arrive every ~4 cycles"; that
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// was wrong — the 4:1 ratio applies between clk_400m and clk_100m, not as
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// further sub-sampling within clk_100m.
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//
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// Implication: this 32-tap FIR's cutoff was designed for a 25 MSPS rate
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// (the post-decimation rate that "every 4 cycles" would imply). Running
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// at 100 MSPS shifts the effective cutoff 4× above that. The system's
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// existing tests pass because the 36-bit accumulator silently wraps on
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// large sustained inputs (giving lowpass-like behaviour by accident) —
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// see the build report and the open RX-NEW-3 design question. Any future
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// DSP-saving rework of this module needs a designer call on the
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// rate-vs-coefficient mismatch.
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// ============================================================================
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// Filter coefficients (symmetric: coeff[k] == coeff[31-k])
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reg signed [COEFF_WIDTH-1:0] coeff [0:TAPS-1];
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// Parallel delay line
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reg signed [DATA_WIDTH-1:0] delay_line [0:TAPS-1];
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// Parallel multiply results (combinatorial)
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wire signed [DATA_WIDTH+COEFF_WIDTH-1:0] mult_result [0:TAPS-1];
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// Pipelined adder tree registers
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// Level 0: 16 pairwise sums of 32 products
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reg signed [ACCUM_WIDTH-1:0] add_l0 [0:15];
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// Level 1: 8 pairwise sums
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// USE_DSP="no" forces pure additions to fabric CARRY4 chains, freeing DSP48E1
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// slices for the FFT butterfly multipliers that otherwise spill to 18-level
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// fabric carry chains causing timing violations on the XC7A50T (120 DSP budget).
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(* USE_DSP = "no" *) reg signed [ACCUM_WIDTH-1:0] add_l1 [0:7];
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// Level 2: 4 pairwise sums
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(* USE_DSP = "no" *) reg signed [ACCUM_WIDTH-1:0] add_l2 [0:3];
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// Level 3: 2 pairwise sums
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(* USE_DSP = "no" *) reg signed [ACCUM_WIDTH-1:0] add_l3 [0:1];
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// Level 4: final sum
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(* USE_DSP = "no" *) reg signed [ACCUM_WIDTH-1:0] accumulator_reg;
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// Valid pipeline: 9-stage shift register (was 7 before BREG+MREG addition)
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// [0]=BREG done, [1]=MREG done, [2]=L0 done, [3]=L1 done, [4]=L2 done,
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// [5]=L3 done, [6]=L4/accum done, [7]=output done, [8]=spare
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// The BREG and MREG stages add 2 cycles of latency.
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reg [8:0] valid_pipe;
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// Initialize coefficients
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initial begin
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// Proper low-pass filter coefficients
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coeff[ 0] = 18'sh00AD; coeff[ 1] = 18'sh00CE; coeff[ 2] = 18'sh3FD87; coeff[ 3] = 18'sh02A6;
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coeff[ 4] = 18'sh00E0; coeff[ 5] = 18'sh3F8C0; coeff[ 6] = 18'sh0A45; coeff[ 7] = 18'sh3FD82;
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coeff[ 8] = 18'sh3F0B5; coeff[ 9] = 18'sh1CAD; coeff[10] = 18'sh3EE59; coeff[11] = 18'sh3E821;
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coeff[12] = 18'sh4841; coeff[13] = 18'sh3B340; coeff[14] = 18'sh3E299; coeff[15] = 18'sh1FFFF;
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coeff[16] = 18'sh1FFFF; coeff[17] = 18'sh3E299; coeff[18] = 18'sh3B340; coeff[19] = 18'sh4841;
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coeff[20] = 18'sh3E821; coeff[21] = 18'sh3EE59; coeff[22] = 18'sh1CAD; coeff[23] = 18'sh3F0B5;
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coeff[24] = 18'sh3FD82; coeff[25] = 18'sh0A45; coeff[26] = 18'sh3F8C0; coeff[27] = 18'sh00E0;
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coeff[28] = 18'sh02A6; coeff[29] = 18'sh3FD87; coeff[30] = 18'sh00CE; coeff[31] = 18'sh00AD;
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end
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// ============================================================================
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// DSP48E1 PIPELINE REGISTERS (BREG + MREG)
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// ============================================================================
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// Vivado DRC warnings DPIP-1 (input not pipelined) and DPOP-2 (output not
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// pipelined) indicate that the DSP48E1 internal BREG and MREG pipeline stages
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// are not being used.
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//
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// Solution: Add explicit registered stages that Vivado can absorb into DSP48E1:
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// BREG: coeff_reg[k] — registered copy of coeff[k], feeds DSP48 B-port
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// MREG: mult_reg[k] — registered multiply output, feeds DSP48 P-port
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//
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// With these registers, Vivado sets BREG=1 and MREG=1 inside DSP48E1,
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// eliminating 68 DPIP-1 + 35 DPOP-2 warnings and improving timing.
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//
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// Pipeline impact: +2 cycles latency (BREG + MREG). Total FIR latency
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// goes from 7 to 9 cycles. Transparent relative to downstream processing
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// (Doppler/MTI operate on accumulated frames, not per-sample).
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// ============================================================================
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// Registered coefficients (BREG — absorbed into DSP48E1 B-port register)
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reg signed [COEFF_WIDTH-1:0] coeff_reg [0:TAPS-1];
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// Registered multiply outputs (MREG — absorbed into DSP48E1 M-register)
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reg signed [DATA_WIDTH+COEFF_WIDTH-1:0] mult_reg [0:TAPS-1];
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// Combinatorial multiply (between BREG and MREG)
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wire signed [DATA_WIDTH+COEFF_WIDTH-1:0] mult_comb [0:TAPS-1];
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genvar k;
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generate
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for (k = 0; k < TAPS; k = k + 1) begin : mult_gen
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assign mult_comb[k] = delay_line[k] * coeff_reg[k];
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end
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endgenerate
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// mult_result now comes from the registered multiply output (MREG stage)
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genvar m;
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generate
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for (m = 0; m < TAPS; m = m + 1) begin : mult_alias
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assign mult_result[m] = mult_reg[m];
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end
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endgenerate
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integer i;
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// ============================================================================
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// Pipeline Stage 0: Shift delay line on data_valid
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// Sync reset: enables DSP48E1 AREG/BREG absorption for delay_line registers
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// feeding the multipliers. Async reset (FDCE) prevented Vivado from using
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// the DSP48E1 internal A/B pipeline registers — the source of 2,522 DPIR-1
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// methodology warnings in Build 9. Converting to sync reset (FDRE) allows
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// Vivado to absorb these into DSP48E1 AREG/BREG, further reducing LUT count.
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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delay_line[i] <= 0;
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end
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end else if (data_valid) begin
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for (i = TAPS-1; i > 0; i = i - 1) begin
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delay_line[i] <= delay_line[i-1];
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end
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delay_line[0] <= data_in;
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end
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end
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// ============================================================================
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// Pipeline Stage 0b (BREG): Register coefficients
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// Runs on data_valid alongside delay_line shift.
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// Vivado absorbs into DSP48E1 B-port pipeline register (BREG=1).
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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coeff_reg[i] <= 0;
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end
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end else if (data_valid) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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coeff_reg[i] <= coeff[i];
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end
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end
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end
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// ============================================================================
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// Pipeline Stage 0c (MREG): Register multiply outputs
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// Captures combinatorial multiply results one cycle after BREG.
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// Vivado absorbs into DSP48E1 M-register (MREG=1).
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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mult_reg[i] <= 0;
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end
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end else if (valid_pipe[0]) begin
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for (i = 0; i < TAPS; i = i + 1) begin
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mult_reg[i] <= mult_comb[i];
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end
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end
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end
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// ============================================================================
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// Pipeline Stage 1 (Level 0): Register 16 pairwise sums of 32 multiply results
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// Each addition is a single 36-bit add — one DSP48E1 hop (~1.7ns), fits 10ns.
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// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
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// Now uses mult_result (from mult_reg/MREG stage) instead of combinatorial multiply.
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < 16; i = i + 1) begin
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add_l0[i] <= 0;
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end
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end else if (valid_pipe[1]) begin
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for (i = 0; i < 16; i = i + 1) begin
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// mult_result is (DATA_WIDTH + COEFF_WIDTH) = 36 bits = ACCUM_WIDTH,
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// so no sign extension is needed. Direct assignment preserves the
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// signed multiply result. (Fixes Vivado Synth 8-693 "zero replication
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// count" warning from the original {0{sign_bit}} expression.)
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add_l0[i] <= mult_result[2*i] + mult_result[2*i+1];
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end
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end
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end
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// ============================================================================
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// Pipeline Stage 2 (Level 1): 8 pairwise sums of 16 Level-0 results
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// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < 8; i = i + 1) begin
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add_l1[i] <= 0;
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end
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end else if (valid_pipe[2]) begin
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for (i = 0; i < 8; i = i + 1) begin
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add_l1[i] <= add_l0[2*i] + add_l0[2*i+1];
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end
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end
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end
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// ============================================================================
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// Pipeline Stage 3 (Level 2): 4 pairwise sums of 8 Level-1 results
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// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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for (i = 0; i < 4; i = i + 1) begin
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add_l2[i] <= 0;
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end
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end else if (valid_pipe[3]) begin
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for (i = 0; i < 4; i = i + 1) begin
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add_l2[i] <= add_l1[2*i] + add_l1[2*i+1];
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end
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end
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end
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// ============================================================================
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// Pipeline Stage 4 (Level 3): 2 pairwise sums of 4 Level-2 results
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// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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add_l3[0] <= 0;
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add_l3[1] <= 0;
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end else if (valid_pipe[4]) begin
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add_l3[0] <= add_l2[0] + add_l2[1];
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add_l3[1] <= add_l2[2] + add_l2[3];
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end
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end
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// ============================================================================
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// Pipeline Stage 5 (Level 4): Final sum of 2 Level-3 results
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// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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accumulator_reg <= 0;
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end else if (valid_pipe[5]) begin
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accumulator_reg <= add_l3[0] + add_l3[1];
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end
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end
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// ============================================================================
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// Pipeline Stage 6: Output saturation/rounding (registered)
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// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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data_out <= 0;
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data_out_valid <= 0;
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end else begin
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data_out_valid <= valid_pipe[6];
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if (valid_pipe[6]) begin
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// Output saturation logic
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if (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) begin
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data_out <= (2**(DATA_WIDTH-1))-1;
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end else if (accumulator_reg < -(2**(ACCUM_WIDTH-2))) begin
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data_out <= -(2**(DATA_WIDTH-1));
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end else begin
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// Round and truncate (keep middle bits)
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data_out <= accumulator_reg[ACCUM_WIDTH-2:DATA_WIDTH-1];
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end
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end
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end
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end
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// ============================================================================
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// Valid pipeline shift register (9-stage for BREG+MREG+5-level adder+output)
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// Sync reset — no DSP48 involvement but keeps reset style consistent with datapath
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// ============================================================================
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always @(posedge clk) begin
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if (!reset_n) begin
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valid_pipe <= 9'b000000000;
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end else begin
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valid_pipe <= {valid_pipe[7:0], data_valid};
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end
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end
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// Always ready to accept new data (fully pipelined)
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assign fir_ready = 1'b1;
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// Overflow detection
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assign filter_overflow = (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) ||
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(accumulator_reg < -(2**(ACCUM_WIDTH-2)));
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endmodule
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