Jason 6af79f9c74 fix(fpga): TX range-mode awareness + clamp reserved host codes ...

C-1: plfm_chirp_controller was not range_mode-aware; it always ran
LONG_CHIRP for CHIRP_MAX/2 chirps even when the host selected 3 km
mode, where the ~4.5 km blind zone exceeds the 3 km max range and
pollutes the RX window. IDLE now branches straight to SHORT_CHIRP
when range_mode == RP_RANGE_MODE_3KM. host_range_mode is passed from
radar_system_top through radar_transmitter, CDC'd per-bit from
clk_100m to clk_120m_dac (coherency-safe: reserved codes are clamped
at the source so only bit[0] toggles).

S-3: opcode 0x20 now clamps reserved range-mode codes (2'b10, 2'b11)
to the 3 km default so a garbled host write cannot silently enable
long-range TX behaviour.

Regression: tb_chirp_controller adds a 3 km-mode group (5 checks)
verifying IDLE->SHORT_CHIRP skip path and DONE after CHIRP_MAX short
chirps; tb_system_e2e G14 labels updated for clamped reserved codes.
32/32 regression PASS (50/50 on chirp TB).

2026-04-22 20:26:43 +05:45

..

9_1_Microcontroller

refactor(mcu): remove redundant ADAR1000 T/R SPI paths (FPGA-owned)

2026-04-21 01:09:38 +05:45

9_2_FPGA

fix(fpga): TX range-mode awareness + clamp reserved host codes

2026-04-22 20:26:43 +05:45

9_3_GUI

fix(gui): align radar parameters to FPGA truth (radar_scene.py)

2026-04-16 21:35:01 +05:45

tests/cross_layer

test(fpga): F-3.2 add DDC cosim fuzz runner with seed sweep

2026-04-20 15:48:34 +05:45

tools

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