Jason 5617d552df fix(fpga): frame-boundary atomic commit for USB timing regs ...

C-4: GUI Waveform Timing opcodes (0x10..0x14) write one parameter per
USB packet with arbitrary inter-opcode latency. Previously each opcode
landed directly on a live register consumed by radar_mode_controller,
so a mid-scan reconfiguration exposed the RX FSM to torn sets (e.g.
new long_chirp with old long_listen), and a value below the running
timer truncated the current chirp and corrupted one range-Doppler
frame.

Fix: split each of the five timing regs into pending (USB write target)
and live (FSM consumer). radar_mode_controller exports a new
cfg_commit_strobe that is HIGH while scanning is idle (S_IDLE) and
pulses for 1 cycle at every elevation/azimuth boundary in S_ADVANCE.
radar_system_top snapshots pending -> live on the strobe, guaranteeing
the FSM always sees a self-consistent set. No CDC added: strobe is in
clk_100m same as the USB-cmd path.

Regression: tb_radar_mode_controller adds 3 checks for strobe
semantics (idle-HIGH, scanning-LOW, one pulse per elevation boundary).
32/32 full regression PASS; Radar Mode Controller TB grows from 78 to
81 checks.

2026-04-23 04:43:02 +05:45

..

9_1_Microcontroller

refactor(mcu): remove redundant ADAR1000 T/R SPI paths (FPGA-owned)

2026-04-21 01:09:38 +05:45

9_2_FPGA

fix(fpga): frame-boundary atomic commit for USB timing regs

2026-04-23 04:43:02 +05:45

9_3_GUI

fix(gui): align radar parameters to FPGA truth (radar_scene.py)

2026-04-16 21:35:01 +05:45

tests/cross_layer

test(fpga): F-3.2 add DDC cosim fuzz runner with seed sweep

2026-04-20 15:48:34 +05:45

tools

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